Case Studies in Atomic Force Probe Analysis
R. E. Mulder1, S. Subramanian2, T. Chrastecky2, (1)Silicon Labs, Austin, TX, (2)Freescale Semiconductor, Inc., Austin, TX
The use of Atomic Force Probe (AFP) analysis in the analysis of semiconductor devices is expanding from its initial purpose of solely characterizing CMOS transistors at the contact level. Other uses of the AFP tool include the full analysis of failing SRAM bit cells, current contrast imaging of SOI transistors, the probing of metallization layers to measure via stack resistance, and use with other tools, such as light emission, to localize and identify defects in logic circuits. This paper will present several case studies in regards to these activities and their results.
FA/LIT Instrument Adjustments for Successful Analysis of Packaged Semiconductor Devices
D. J. D. Sullivan1, S. Hsiung1, J. Soopikian2, (1)LSI Logic, Fremont, CA, (2)LSI Logic Corporation, Fremont, CA
The laser ablation tool, FA/LIT, parameters required for successful use are dependent on the sample materials and require trail and error testing to determine. As set of succesful tests are shown along witht he need for sample grounding in the instrument.
Coupling C-AFM with Nano-Probing Technique for Further Junction Leakage Analysis
C. M. Shen1, T. C. Chuang2, C. M. Huang2, S. C. Lin2, J. F. Chang2, (1)Taiwan Semiconductor Manufacture Company, Ltd., Taiwan, Hsin-Chu, Taiwan, (2)Taiwan Semiconductor Manufacture Company, Ltd., Tainan, Taiwan
To couple C-AFM and Nano-probing would be able to acquire more electrical information to help concretizing ratiocination based on the characteristic of semiconductor device. In our experiment, the most significant matter was to reveal the inside story of faking junction or gate leakage. And a cunning defect hidden at the corner of active region and STI was discovered by this methodology.
Mixed-Signal Test Software Generation Process – Open Environment, Software Engineering Methods and Tools for Improving Quality and Productivity
S. Vock, SEPT Europe, Baierbrunn, Germany
The huge code base of nowadays mixed-signal test programs is a significant challenge for the code generation productivity and for maintaining code quality which inherently translates into outgoing quality. This paper will present how the adoption of software engineering methods can address these challenges.
Conductive Atomic Force Microscopy Application for Semiconductor Failure Analysis in Advanced Nanometer Process
C. Lin1, S. S. Lu2, H. Zhang3, (1)No.3 Li-Hsin Rd. II , Science-Based Industrial Park, Hsin-Chu City,Taiwan 300, R.O.C., Hsin-CHu,Taiwan, Taiwan, (2)National Taiwan University, Taipei, Taiwan, R.O.C, Taiwan, (3)Failure Analysis dept, Product Division, UMCi, Singapore, Hsinchu, Singapore
Conductive Atomic Force Microscopy (C-AFM) is an accurate and useful tool for both electrical failure analysis (EFA) and physical failure analysis (PFA).
Laser Based Analysis on Analog Circuits With Feedback Loops and a Case Study
F. Zhang, D. Maxwell, Texas Instruments Inc., Dallas, TX
Based on the understanding of laser based techniques’ physics theory and the topology/structure of analog circuit systems with feedback loops, the propagation of laser induced voltage/current alteration inside the analog IC is evaluated. A setup connection scheme is proposed to monitor this voltage/current alteration to achieve a better success rate in finding the fail site or defect. Finally, a case of successful isolation of a high resistance via on an analog device is presented.
A Novel Method to Inspect Deep Trench Capacitor Planar Profiles in DRAM
J. L. Lue, A. Huang, T. Wang, ProMOS Technologies Inc., Hsinchu, Taiwan
A novel approach has been developed for determining planar profiles of Deep Trench (DT) Capacitors at any particular depths using mechanical polishing instead of FIB milling method for process monitoring, development, and failure analysis. The sample is polished at a small beveled angle and then is inspected in SEM. This method not only provides a quick way for the inspection of DT planar profiles at any depths in detail but also inspects the DTs in a much larger area than has ever been seen before;the variation in the overall DT profile can be examined within one beveled surface. In addition, this technique is simple to use and it is very cost effective because the FIB is not needed.
Surface Defect Analysis by Using a Novel Backside XTEM Sample Preparation Method
J. S. Luo, L. Y. Huang, W. L. Gu, J. D. Russell, Inotera Memories, Inc., Taoyuan, Taiwan
Transmission electron microscopy (TEM) is more and more important on the structure analysis and characterization of materials for process evaluation and failure analysis in Integrated Circuit (IC) industry with device shrinkage. The sample preparation is critical to TEM analysis success. In general, most of TEM analyses were performed on cross section TEM (XTEM) samples, for instance, line monitoring, construction analysis, embedded defects analysis, etc. Therefore, efficient XTEM sample preparation is essential to TEM analysis for semiconductor industry to perform yield improvement and metrology monitoring. At present, there are many methods to be used to prepare XTEM samples. Among those sample preparation methods, FIB milling using Ga ions is widely used in sample preparation for scanning electron microscopy (SEM) and TEM analysis, especially in localization and investigation of failures or defect analysis. In general, a protection layer, such as Pt or oxide layers, has to be deposited onto specific area using FIB for avoiding ion damage, curtain effect and to reduce the amount of rounding of the top of a TEM lamella during FIB milling. However, a 20-30 nm mixing amorphous layer was formed at the interface of the protection layer and sample. It is a problem to analyze the surface defect or structure, which is just a few nm or less thick on the surface, because the defect or structure will be changed or damaged during a protection layer deposition. Backside polishing is a good choice to overcome the mixing or damage layer. In this paper, a novel method of XTEM sample preparation is demonstrated for specific surface defect analysis using backside polishing. Using our novel sample preparation method, a whole surface defect or structure was localized and then analyzed by TEM successfully. The details of new backside XTEM sample preparation method and few more examples will be carried out in this full paper.
Application of EDS Technique for OSP Film Thickness Measurement
P. Kongsubto, S. Kongwudthiti, K. Kamthongsuk, Spansion (Thailand) Ltd., Nonthaburi, Thailand
Nowadays, the technique for OSP thickness measurement is UV-Spectrophotometer method. Unfortunately, the OSP coating on substrate pad has too small amount to obtain the accurate results from this method so another possible technique will be studied. In this work, we aim to evaluate the possibility of EDS quantitative analysis technique for OSP thickness measurement purpose. The statistical tool was also applied in selecting the setting parameter for EDS analysis and in fitting the curve to initiate the equation for OSP thickness estimation. The obtained EDS analysis data is in terms of %C to % Cu (C/Cu ratio). We success on establishment the relationship between C/Cu ratio and actual OSP thickness as follow: Thickness = -0.024 + 0.34199(C/Cu) – 0.02498(C/Cu)^2. From this equation, once the C/Cu value was obtained by EDS method, then the OSP thickness can be readily calculated.
Applications of Transmission Electron Microscopy and Secondary Ion Mass Spectrometry on Crystal Defect Analysis and Electronic Characterisation of Advanced 512 Mb DRAM
J. S. Luo, Y. H. Lu, P. Y. Chen, J. D. Russell, Inotera Memories, Inc., Taoyuan, Taiwan
The transmission electron microscope (TEM) plays a very important role in the ultra-thin film monitoring and material science analysis with high resolution as the device shrinkage, especially on atomic level crystal defect analysis. From our present observations, more and more device leakage problems are related to crystal defects, such as dislocation, dislocation loop and stacking faults. Especially, those defects appearing at P-N junction or around source and drain areas of transistors. Normally, these crystal defects were believed to be induced by the implantation process. In addition, it is well known that the device’s performance and characteristics are very dependent on the implanted dosage and resulting profile shape. For instance, the threshold voltage (Vth) of MOSFETs decreases as the channel length is shortened and also as the drain bias is increased. The influencing factors of Vth performance are device geometry, doping, gate oxide thickness and interface charge fluctuations. Secondary Ion Mass Spectrometry (SIMS) has the same sensitivity as the electrical test data of Vth on the dose variation. For deep trench (DT) type DRAM, As is used to be a dopant in poly-Si electrodes or Si substrate electrodes of memory cell for reducing the electrode’s resistance. The As distribution, which near the interface of AA and doped poly-Si, is very important. Because it might influence the drain implanted profile and channel, which cause Vth mis-matching, when As diffuses to the drain area. Furthermore, the micro-structure in doped poly-Si grains will also influence device performance. In this letter, we report several examples to carry out the applications of TEM and SIMS on crystal defects analysis and electronic characteristics of advanced 512M- bit DRAM.
Advanced Manual Package Pulling System for Removing PCB Components in Preparation for Crack Area Measurement and Disbond Type Mapping
T. R. McDonald, Intel, Hillsboro, OR
With the increased use of crack are measurment and disbond type mapping metrologies, Manual pull tools have become a preffered quick method to separate board components. Since recording force curves is not typically required for this type of work, Engineers have turned to simple deivces that require little set up or expense to remove components. Tools such as flat head screw drivers, facbricated pry tools and cam lever devices have been used to accomplish separation. Some designs make contact with some solder joints, others apply removal force unevenly across the solder joints that could compromise data, and most present safety and ergonomic risk to the operator. The manual pull tool system introduced here, demonstrates a dramatic reduction of these concerns
Application of FIB Circuit Edit in Analysis of Memory Failure of SOI Devices
Z. Song1, S. K. Loh2, X. H. Zheng2, S. P. Neo2, C. K. Oh2, (1)IBM, Hopewell Junction, NY, (2)Chartered Semiconductor Mfg Ltd, Singapore, Singapore
SOI technology poses new challenges on failure analysis. For bulk silicon technology, contact-level Passive Voltage Contrast (PVC) is a powerful technique for memory failure. It can easily identify the open active contact from the normal active contacts. However, for SOI technology, active contacts land on T-Si, which is insulated from silicon substrate. Whether active contacts are open or not, they are at the same potential under e-beam or ion beam inspection because they are all floating. So, contact-level PVC technique is not suitable for SOI technology. In this paper, we will present some cases to demonstrate the application of FIB circuit edit in analysis of memory failure of SOI devices.
A Fast Inspection of Well Implantation by Using Plane-View Stain Method
J. C. Lin, -. W. S. Wu, -. K. S. Chen, J. H. Yeh, Y. C. Hou, United Microelectronics Corporation, Hsin-Chu, Taiwan
Front-end implantation failure issue is always very difficult to do FA especially in full process wafers. This is because implantation failure at specific area is almost structure invisible by SEM and FIB inspections. With the help of plane-view stain technique, a fast preview at the suspected Well regions can be done by 30 sec’s plane-view stain and SEM plane-view check. This new developed technique can greatly shrink the FA cycle time and avoid the unnecessary job of specific SCM. Unlike traditional X-S stain, the difficulties of sample preparation at the specific site and precise stain time control can be completely eliminated. Besides, one Pt-coated film on X-S sample surface before SEM observation is unnecessary by using plane-view stain method.
Solder Ball Removal Method for Flip Chip with Ceramics in Microelectronic Package
S. T. I., C. Tung Hung, United Microelectronics Corporation, Hsinchu, Taiwan
This paper will provide an alternative methodology to deacp of Flip chip package type of semiconductor microelectronic device by manual method and chemical reaction of some acid. By the process can be used to consistently and accurately prepare of flip chip while reducing consumables usage and saving preparation time to increase sample throughput and improve surface finishes.
Note on the Use of Principal Component Analysis ( PCA) and Clustering for the Analysis of Wafer Level ATPG Data
K. Ramanujachar1, S. Draksharam2, (1)Intel Corporation, Chandler, AZ, (2)Texas Instruments, Stafford, TX
In this contribution we explore the use of Principal Component Analysis and hierarchical clustering in the analysis of wafer level ATPG ( automatic test pattern generation) failure data. The method outlined will enable the selection of representative samples for physical failure analysis (PFA) following fault isolation with automated scan based software tools like Fast scan or Tetramax.
Failure Analysis Navigation System Connecting Hardware Analysis to Software Diagnosis
A. Shimase1, A. Uchikado1, Y. Matsumoto1, S. Watarai1, S. Kawanabe1, T. Suzuki1, T. Majima1, K. Hotta2, T. Hirotoshi2, (1)Renesas Technology Corp., Kodaira-shi, Japan, (2)Hamamatsu Photonics K.K., Hamamatsu-shi, Japan
A newly developed failure analysis assisting system can pick out the nets passing through the reactions detected in hardware analysis equipments, such as an emission microscope or an OBIRCH analysis system, and it can collate these nets to the doubtful nets extracted by software diagnosis to select the most doubtful net. This paper introduces the functions of the system and shows some case studies in actual failure analyses.
Usage of SAM on Fatigue Crack of Solder Joint Induced by Thermal Reliability Test
T. H. Chen, T. I. Shih, United Microelectronics Corporation, Hsinchu, Taiwan
Thermal fatigue crack of lead-free solder joint within flip-chip package was investigated in this study by using scanning acoustic microscope (SAM) and SEM. The distribution of substrate delamination were mapped with the SAM of high depth resolution and observed with X-section SEM to find the mechanism of crack growth during the thermal reliability test.
Laser Based Defect Localization for the Failure Analysis of Advanced Product
W. Y. Cheng, Taiwan Semiconductor Manufacturing Company, Hsin-Chu, Taiwan
Several methods and tools have been used for FA defect isolation; emission microscopy (EMMI) is the most popular tool among these techniques. But for advanced products, the working voltage is getting more and more small, thus many emission spots from normal transistors will be observed, which indeed impacts the judgment on the emission spots from real defects and increases the FA difficulty. Laser scanning microscopy has been a common technique for failure site isolation for these years, which can detect some defects that is not easy to catch by EMMI such as higher resistance, short and S/D contact open. Furthermore, the defects are at the same locations of spots that reduce much time for layout tracing before PFA.
Enhanced Detection Sensitivity with Pulsed Laser Digital Signal Integration Algorithm
A. Quah1, L. Koh2, S. Tan2, C. Chua2, J. Phang1, (1)National University of Singapore, Singapore, Singapore, (2)SEMICAPS PTE LTD, Singapore, Singapore, Singapore
A pulsed laser signal integration algorithm has been developed for sensitivity enhancment in laser induced techniques. Sensitivity is enhanced by a gain factor of 3 times
A Study of Flip-Chip Open Solder Bump Failure Mechanism
Z. Wang, M. Chouhdry, International Rectifier, Temecula, CA
Solder bump de-lamination failure mechanism is studied in depth. Evidence of de-lamination between bond pad metal and TiW layer and fracture within the Al layer, evidence of initial fracture at the bump neck due to nitride film stress are collected. The failure mechanism is concluded to be preexisting defective/weak bump interface activated by cyclic stress under ultrasonic wash during module assembly process.
Non-Destructive Method for Detecting Solder Defects at the Second Level Interconnect Using 3D X-Ray Tomography (uCT)
F. Toth1, G. F. Shade2, (1)Intel Corporation, Hillsboro, OR, (2)Intel, Hillsboro, OR
Describes non-destructive solder joint analysis technique to detect mode "H" failures at the second level interconnect on PCB assemblies. The 3D Xray tomography method can relace destructive analysis techniques used up until now such as cross section analysis. Results of Xray data and destructive methods correlate 100%.
Deformation Study of Low K Dielectric after E-Beam Exposure
X. Chen1, Q. Gao2, M. Li3, C. Niou4, K. Chien3, (1)Semiconductor Manufacturing International (Shanghai) Corp, Shanghai, China, (2)Semiconductor Manufacturing International Corporation, Shanghai, China, (3)Semicoductor Manufacturing International Co., Shanghai, China, (4)Semiconductor Manufacturing International (Beijing) Corp, Beijing, China
In this work, deformation mechanism of low K dielectric film under E-beam was discussed. And the influence of deformation on low K dielectric film etching recipe development was investigated. To provide meaningful data for process development, numerical analysis was introduced to failure analysis procedure. A correction factor was applied to calculate and modify the true value of low K dielectric film thickness after E-beam exposure. SEM analysis conditions for imaging low K dielectric film were optimized to decrease deformation.
Realization of an Integrated IT System Covering the Complete Failure Analysis Process
M. Grützner, Infineon Technologies AG, Munich, Germany
In many parts of the failure analysis process software tools are involved: Lab management using job lists, creation of report documents, handling of image files and many more. Having all these functions integrated in one single tool can greatly improve an FA lab’s working process. This paper describes the process and result of developing a dedicated FA tool for a major semiconductor company.
New Approach: Sample Preparation Techniques for Plastic Small Outline Package (front-side and backside)
E. Marquez1, T. To2, D. Nguyen2, (1)Texas Intruments, Inc., Dallas, TX, (2)Texas Instruments Inc., Dallas, TX
In this paper, two sample preparation techniques for Small Outline Package (SOP) will be presented. The first technique is for front side sample preparation. A new procedure on jet etching system decapsulator was developed specially for small outline package device. The encapsulant will be removed while preserving the integrity of the die, bond pads, bond wires and lead frame interconnects. In addition, we will show a method eliminate the needs for repackaging on backside sample preparation. Both techniques allows failure analyst to do both front side or backside analysis on any small package devices
The Electrical Characterization and Physical Failure Analysis for Transistor Gate Leakage
T. T. Li1, C. C. Wu1, J. H. Chuang1, J. C. Lee2, (1)Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, Taiwan, (2)Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, Taiwan
In this case, FA was performed for soft failure single bit. A suspected transistor with gate to source/drain leakage was isolated by a preliminary analysis with C-AFM, which has been widely used for the failure analysis of advanced semiconductor products. And for getting more information to realize the failure behavior and mechanism of the suspected transistor, a powerful tool, Nano-probing was used to measure the electrical behavior of a single device for the further analysis. The Id-Vg behavior of the suspected transistor was significantly different from that of reference transistor. Exchanging the voltage sweep of source and drain, the Id-Vg behavior was similar between suspected and reference transistor. Furthermore, gate leak to S/D of suspected transistor was observed from the current components of Ioff I-V curve. The asymmetry I-V behavior means that the gate leak only happened on one node of S/D. In order to double confirm the Nano-probing result and the hypothesis of gate oxide leakage, the simulation data of a gate-leak-to-S/D transistor was compared with Nano-probing data, the result of Id-Vg behavior was almost the same. A local gate oxide anomaly of this gate-leak-to-S/D transistor was observed from X-section TEM images. And a further approach to reveal the leakage point was implemented. Purposed over stress with appropriate voltage bias was applied between the leaky gate and S/D node to make the leakage point a bit burnout, and then 10%wt KOH was used to etch poly-Si and expose gate oxide for observation on the burnout leakage point.
Failure Analysis of Laser Blown Fuse Failures in Submicron Technology by C-AFM
L. F. Wen, C. H. Chen, A. T. Chang, TSMC, Hsin Chu, Taiwan
The purpose of this paper is to present an electrical analysis skill of submicron technology metal fuse laser blown fail by C-AFM. In order to obtain correct I-V curve data without damaging the failure site, we propose a new method to preserve the fail blown fuses by using SOG coating, and drying etching method to reveal the metal for C-AFM measurement.
Combine Nano-Probing Technique with Difference Analysis to Identify Non-Visual Failures
C. M. Shen1, T. C. Chuang2, J. F. Chang2, J. H. Chou2, (1)Taiwan Semiconductor Manufacture Company, Ltd., Taiwan, Hsin-Chu, Taiwan, (2)Taiwan Semiconductor Manufacture Company, Ltd., Tainan, Taiwan
This paper is to present a novel methodology, which is accomplished by applying difference analysis to Nano-probing technique. And the deductive method was developed to focus on resolving invisible failure modes that could not be characterized by common parameter measuring of Nano-probing nor checking of junction behavior.
A Technique for Reliably Preparing Full-Length Metallographic Cross-Sections of Integrated Circuit Bond Wires
C. M. Nail, Independent, San Jose, CA
This technique uses radiographs as an aid to plotting and adjusting a metallographic plane of section to precisely expose a bond wire across its entire length.
130nm Backend Reliability Failures: Analysis to Corrective Action
G. A. Garteiz, A. Zylberman, Tower Semiconductor, Migdal Ha'emek, Israel
This is a case study showing a 130nm systematic backend reliability failure, its analysis, and corrective action for the line.
Rapid Yield Learning with Effective Integration of FMEA design for DOE on Test Chip
I. A. N. Goh, R. McMullan, B. Fairchild, Texas Instruments Inc., Dallas, TX
As semiconductor technology advances from one node to the next, fabrication also becomes increasingly challenging to ramp up production with the most desirable yield and reliable product in a timely manner. At an advanced technology node such as 65nm, the interaction between product design, process margin, and process equipment continues to limit the product yield and reliability performance. Traditional methods, which usually rely on sequential feedback of each experimental lot, require too many learning cycles to achieve target performance, yield, and reliability levels. This paper describes a methodology that potentially accelerates the progression of identifying process and product-design interactions and marginalities during the development stage. Not only can this methodology result in a quicker ramp to production, it also has the benefits of improving costs, yield, and reliability.
Secondary Electron Potential Contrast for Dopant Profiling of Silicon Carbide Devices
M. Buzzo1, M. Ciappa2, W. Fichtner2, (1)Infineon, Villach, Austria, (2)Swiss Fedeal Institute Of Technology Zurich, Zurich, Switzerland
Recent publications reported a surprisingly intensive dopant contrast arising in Secondary Electron SEM images of Silicon Carbide devices. This work gives an insight into the physics of the contrast generation and discusses the proper experimental setup to be used for the quantitative two-dimensional delineation of bipolar and homojunctions in Silicon Carbide devices.
Image Intensity Analysis for Defect Localization Utilizing SEM BSE Imaging
J. J. Demarest1, K. Chanda1, C. Christiansen2, S. Klepeis1, B. Redder1, A. Shore1, Y. Wang3, C. Rue4, (1)IBM, Hopewell Junction, NY, (2)IBM, Essex Junction, VT, (3)Ohio State University, Columbus, OH, (4)FEI Company, Hillsboro, OR
With shrinking defect size and evolving dielectric materials surrounding the metallization placed on today’s state-of-the-art computer chips, failure analysts occasionally find themselves faced with the task of identifying defects which are effectively rendered invisible to the human eye. The physics of the various isolation techniques which are available clearly indicate the presence of a defect within a certain region. However, inspection of that area with conventional techniques such as secondary electron and back scattered electron (BSE) scanning electron microscopy (SEM) does not lead to physical defects being readily apparent in the images obtained. Exploitation of subtle variations in intensity through intensity profiling can localize defects which would otherwise not be observed by comparison to healthy reference structures in adjacent locations on the sample. Both resistive shorts and resistive opens will be discussed through illustrative case studies demonstrating this technique at the 130 nm and 65 nm technology nodes in low-k dielectric materials.
Focused Ion Beam Grounding to Alleviate Sample Charging for Scanning Auger Electron Spectroscopy
E. Morales, C. F. H. Gondran, ATDF at International SEMATECH, Austin, TX
we describe the application of the FIB spot mill grounding technique to sample preparation for AES. This is a quick, clean, and effective method to avoid charge buildup on samples requiring AES analysis.
Energy Dispersive Spectrum (EDS) Study of Copper Grid Effect on Semiconductor Failure Analysis
J. Hu1, M. Li2, Q. Qao1, C. Niou3, K. Chien2, (1)Semiconductor Manufacturing International Company, Shanghai, China, (2)Semicoductor Manufacturing International Co., Shanghai, China, (3)Semiconductor Manufacturing International (Beijing) Corp, Beijing, China
In this paper the artifacts of additional copper signal induced by copper grid, one of the most widely used supporting grid for FIB (focus ion beam) prepared TEM sample, was studied. Its influence on both spot and line scan EDS analysis was described. It was found that in line scan analysis the copper signals changed between heavy and light elements, which could bring confusions to the EDS analysis on Cu interconnect structure. Based on the study on nickel-supported film, we concluded that the additional copper signals mainly result from electrons scattered by the sample striking the Cu grid.
Studies of Silicon Dust Corrosion on Microchip Al Bondpads and Elimination of Silicon Dust During Wafer Sawing Process
Y. N. Hua1, S. P. Zhao2, (1)GLOBALFOUNDRIES Singapore Pte Ltd, Singapore, Singapore, (2)Chartered Semiconductor Mfg Ltd., Singapore, Singapore
Galvanic corrosion may result in discolored or non-stick bondpad problem. In authors’ previous studies [Hua et al, ISTFA 1998 and ISTFA 2000], theory, characteristics and eliminating solutions of galvanic corrosion have been discussed. It is well-known that after wafer-die sawing process, sometime Si dust is difficult to be cleaned away by DI water, especially at pinhole/corrosive areas caused by galvanic corrosion, thus resulting in NSOP at the assembly houses. It is also noted that Si dust has made significant contribution to NSOP. However, till now, the mechanism is not fully understood and there isn’t a suitable theory to explain it. To eliminate NSOP due to Si dust, it is necessary to further study the mechanism. In this paper, we will study the mechanism of Si dust contamination, and propose the concept of Si dust corrosion. After studying, a theoretical model will be introduced so as to explain Si dust contamination problem during wafer die sawing process, and then discuss the eliminating methods of Si dust on microchip Al bondpads during wafer-die sawing process. After studying, we propose the below mechanism: DI H2O related process enhances galvanic corrosion -> Generate new corrosive product [OH]- ions -> [OH]- causes Si dust corrosion -> Form Si Gel-like materials (nSiO2.nH2O) -> NSOP Based on the above mechanism model, we think that if galvanic corrosion occurs on Al bondpads during wafer die-sawing process, [OH]- ions generated from galvanic corrosion will not only react with Al to cause Al corrosion (form Al (OH)3), but also react with Si dust to cause Si dust corrosion. During Si dust corrosion, poly-H2SiO3 and Si-Al-O complex compounds will be formed on Al bondpads at the corrosive areas. During Si duct corrosion, Si dust becomes a “Gel-like” material that has a high level of stickiness and will stick onto the surface of bondpads. “Gel-like” material is insoluble in water and difficult to be cleaned away by DI water during or after wafer die-sawing processes. In this paper, an electrochemical theoretical model (chemical equations) will be presented, which will help us to understand the mechanism of Si dust contamination and Si dust corrosion during wafer die-sawing process so as to find a solution to reduce Si dust on Al bondpads and eliminate NSOP during the assembly processes. TOF-SIMS technique is employed to identify the compounds of Si-O and Si-O-Al and study the mechanism of Si dust corrosion physically and chemically. The eliminating methods of Si dust on microchip Al bondpads during wafer-die sawing process will be introduced and discussed.
Analysis of Delta Iddq Soft Fails on Pass Chips
I. Österreicher1, B. Tippelt2, S. Doering2, R. Prang3, S. Eckl1, W. Werner2, (1)Infineon Technologies Dresden GmbH & Co. OHG, Dresden, Germany, (2)Qimonda Dresden GmbH & Co. OHG, Dresden, Germany, (3)Qimonda Dresden GmbH & Co. OHG, Dresden, Germany
A new class of soft defects was analyzed on chips that proved to be functional under any condition but showed delta Iddq variations at certain scan vectors. The failure analysis flow was adapted to this kind of “soft fails” that may cause potential reliability problems. Physical Failure Localization was performed which showed emission spots at positions that were inconspicuous on dies with constant Iddq consumption. Atomic Force Probing proved a transistor Source-Drain leakage which was obviously not high enough to cause a functional fail but revealed itself in small current variations. The leakage current was attributed to a defective CA-contact interface.
Applications of Soft Defect Localization (SDL) on AMD Advanced SOI Microprocessors
Y. X. Seah, AMD Singapore, Singapore, Singapore
In this paper, we present the application of SDL technique towards full root cause analysis of functional and structural failures such as BIST, SCAN etc on AMD’s advanced Silicon-on-Insulator (SOI) microprocessors based on 90nm process technology node.
Active Voltage Contrast for Failure Localization in Test Structures
R. Rosenkranz1, S. Doering1, W. Werner1, S. Eckl2, L. Bartholomaeus3, (1)Qimonda Dresden GmbH & Co. OHG, Dresden, Germany, (2)Infineon Technologies Dresden GmbH & Co. OHG, Dresden, Germany, (3)Qimonda AG, Munich, Germany
Active Voltage Contrast technique is demonstrated in a SEM/FIB system applied to contact chain test structures. It is shown that AVC enhances SEM/FIB voltage contrast to a level that enables localizing a much broader spectrum of defects.
Floating Substrate Passive Voltage Contrast (FSPVC)
M. W. Jenkins1, P. Tangyunyong1, E. I. Cole Jr.2, J. M. Soden1, J. A. Walraven1, A. A. Pimentel1, (1)Sandia National Labs, Albuquerque, NM, (2)Sandia National laboratories, Albuquerque, NM
Floating substrate passive voltage contrast (FSPVC), like conventional PVC, locates the transistor gates responsible for light emission with much finer resolution than light emission alone and does not require the ground path needed with conventional PVC. Therefore, sample deprocessing/preparation is simplified and the PVC approach can be applied to SOI technologies.
Fault Identification by Use of a Simulated Passive Voltage Contrast Reference CAD Display
R. Fredrickson, On Semiconductor, Gresham, OR
In this paper, a fault identification method is discussed by creating a Simulated Passive Voltage Contrast Reference that can be displayed next to the SEM VC image for a comparison of the expected VC. By comparing the reference image representation to what is seen in the SEM, defective connections can be easily identified. This reference “display” is produced by processing the design’s polygon file (such as a GDS2) through an algorithm that simulates the connections at a given layer to the layers below and outputs a new polygon file (GDS2) with sub-layer markers indicating a ground, gate, or open connection.
SEM and AFM Investigation for Accurate Measurements of 193 nm Resist Profiles
R. Reiche, R. Bartkowiak, M. Heller, R. Rosenkranz, Qimonda Dresden GmbH & Co. OHG, Dresden, Germany
The reliability of SEM measurement data like CD, film thickness and profile shape is very questionable due to the shrinkage of 193 nm photoresist material during electron beam exposure. Especially the analysis of resist profiles after cross section is seen to be critical. The purpose of this study is to investigate and quantify the effect of AuPd sputter preparation and SEM imaging conditions on film thickness, CD and profile shape in order to obtain high reliability and reproducibility of sample preparation and SEM measurement post resist cross section. The original thickness of the patterned 193 nm resist structures is determined from AFM measurements without destructive modification of the resist surface.
A Novel Method for Deep Trench Profile Characterization and Process Monitoring in 90nm DRAM Technology
K. H. Huang, W. L. Gu, M. D. Liu, Y. S. Wang, J. D. Russell, Inotera Memories, Inc., Taoyuan, Taiwan
This method of top-down polishing by pre-tilt angle provides more information compared with traditional cross-section cleaving or top-down polishing. It not only provides precise and varied DT depth structure information, but can also through continuous DT shape measurement, provide accurate data for DT capacitor simulation compared with other methods.
Challenges in Evaluating Thickness, Phase, and Strain in Semiconductor Devices Using High-Resolution Transmission Electron Microscopy
R. Rai, J. Conner, S. Murphy, S. Swaminathan, Freescale Semiconductor, Austin, TX
In this paper, HRTEM challenges related to accurate thin gate oxide measurements, interfacial layer in high-k gate dielectric, strain measurements in Si-Ge MOSFETs, and phase analysis in Ni silicide using HRTEM will be described.
Techniques for Analyzing Solder Joint Properties and Damages in FBGA Packages
S. Leinert1, S. Jansen2, N. Martin1, D. Breuer1, W. Werner3, (1)Qimonda Dresden GmbH Co. OHG, Dresden, Germany, (2)Qimonda Dresden GmbH Co. OHG, Dresden, Germany, (3)Qimonda Dresden GmbH & Co. OHG, Dresden, Germany
Analysis methods, such us solder etching, FIB and TEM imaging, for damage or material analysis in solder joints of FBGA packages are presented. The methods allow a more in depth analysis or result in a clearer idea about the situation especially concerning the intermetallic compound formation at the solder ball - pad - interface.
Back Side Die Preparation for Check of Backend Related Problems
M. Huettinger1, U. Papenberg1, J. Touzel1, A. Janeiro2, R. Guedes2, C. Caldeira2, C. Ribeiro2, P. Rocha2, (1)Infineon Technologies AG, Munich, Germany, (2)Infineon Technologies AG, Mindelo, Portugal
Abstract: Damages on the top metal layer caused by the package processes in the backend result often in not punctual electrical failure like column select fails. So, X-sections through an exact address cannot be performed. Decapping from the front side of the die by removing the package (Top-Down preparation) only uncovers the area with the damaged structures of the die. Any root cause linked with the package is gone. So a preparation preserving the package at the failure (Bottom-Down preparation) is neces-sary. This paper presents a preparation method for investigations and assessment of backend related problems by removal of the Si-die from the back side, letting package and con-nections layers free for a quick and reliable review.
Development of the Polishing Technique for the Observation of the Intermetallic Compound at Solder Joint
P. Kongsubto, S. Kongwudthiti, N. Santipruksawong, J. Tippayamontri, T. Promket, Y. Singsa, K. Kamthongsuk, Spansion (Thailand) Ltd., Nonthaburi, Thailand
Due to the typically low thickness of inter-metallic compound at solder joint so it is difficult to inspect its thickness and characteristic even using SEM. In this study, the sample preparation technique was developed to facilitate the observation of such inter-metallic compound. Polishing medium was investigated to find out the most suitable polishing medium for IMC inspection purpose in both SnPb and Pb-free solder ball. With this technique, microstructure of the inter-metallic layers between Tin and Copper could be easily visualized.
Enhancement Method to Improve the Accuracy of Inter-Metallic Area Inspection on the Bonding Pad through Chemical and Mechanical Removal Processes
K. Kamthongsuk, P. Kongsubto, S. Kongwudthiti, R. Lochingchairit, P. Kongjaroon, Y. Yousoom, Spansion (Thailand) Ltd., Nonthaburi, Thailand
The novel sample preparation method using the combination of sequential mechanical treatments (grinding), and chemical treatments (Potassium Hydroxide- KOH & Dilute Hydrochloric Acid- HF) provides more robust, more accurate and easier to handling with for determining the percentage of inter-metallic formation area formed on the bonding pads of both BGA and lead IC packages structures. Series of experiments with statistical analysis had been conducted to confirm the results.
Functional IC Analysis through Chip Backside with Nano Scale Resolution - E-Beam Probing in FIB Trenches to STI Level
R. Schlangen1, C. Boit2, (1)TUB Berlin Institute of Technology, Berlin, Germany, (2)TUB Berlin University of Technology, Berlin, Germany
The application of E-Beam Probing through chip backside has been demonstrated measuring directly on exposed and electrically isolated transistor actives. The FIB based preparation procedure is reviewed. Presented measurement results are promising for application in nano scale and GHz technology regime.
Use of a Solid Immersion Lens for Thermal IR Imaging
O. Breitenstein1, F. Altmann2, T. Riediger2, D. Karg3, V. Gottschalk4, (1)Max Planck Institute of Microstructure Physics, Halle, Germany, (2)Fraunhofer Institute for Mechanics of Materials, Halle, Germany, (3)Thermosensorik GmbH, Erlangen, Germany, (4)ELMOS Semiconductor AG, Dortmund, Germany
A hemispherical silicon solid immersion lens (SIL) was used to improve the spatial resolution of frontside thermal IR imaging in lock-in mode. The bottom of the SIL was cone-shaped to reduce the footprint of the SIL to the size of the imaged region. Thanks to the lock-in operation mode the detection limit improves by 2-3 orders of magnitude, and scattered light does not limit the image contrast. By using this SIL together with an IR camera working in the 3-5 µm wavelength range, a spatial resolution of 1.4 µm was obtained for thermal IR imaging.
Indirect Electrostatic Discharge Stressing Mechanism in VLSI Chips with Multiple Power Supply Domains
S. Sofer1, Y. Fefer1, Y. Shapira2, (1)Freescale Semiconductor Israel Ltd., Herzelia, Israel, (2)Tel Aviv University, Tel Aviv, Israel
Indirect electrostatic discharge stressing of a chip with multiple isolated power domains was analyzed. The stress penetrates to the victim domain via common nets having non-negligible complex impedance and via coupling of the inter-domain parasitic capacitors and in some cases may cause chip damage.
Planar Deprocessing of Advanced VLSI Devices
K. S. Wills, Independent Consultant, Sugar Land, TX
The use of the OmniEtch tool is explored for the purposes of insuring planer deprocessing of VLSI devices. The chemistries and techniques used will be explored to deprocess from the solder bumps down through the top level of metal. Repetitive use of the same chemistries will permit deprocessing to the substrate.
An Advanced Integrated Circuit Analysis System
E. Keyes, J. Abt, Semiconductor Insights, Ottawa, ON, Canada
A system for the analysis and reverse enigneering of modern, nanometer scale integrated circuits is described.
Translating Yield Learning into Manufacturable Designs
V. Chowdhury, Y. Ada, V. Girish, R. Irfan, Altera Corp., San Jose, CA
Even though manufacturing design rules exist for a production process technology, good manufacturing practice requires that these be constantly reviewed in the light of ongoing learning and experience acquired through failure analysis and yield enhancement efforts.Traditionally, it is the foundries that have been primarily responsible for managing yield. As technologies advance to finer geometries, yield tends to become product specific. A partnership between back end design, failure analysis, EDA4 and fabrication engineers will become increasingly important to achieve yield objectives.
Improving Yield Using Scan and DFT Based Analysis for High Performance PowerPC® Microprocessor
R. Talacka1, C. A. Paquette2, N. Tendolkar1, (1)Freescale Semiconductor, Austin, TX, (2)AMD, Austin, TX
Significant yield improvement requires finding yield issues quickly so process and design fixes can be implemented. Selecting a specific test methodology and using today’s advanced tools like Freescale’s DFT/FA finds more yield issues earlier enabling quicker production releases.
Yield Learning with Layout-Aware Advanced Scan Diagnosis
J. Mekkoth1, M. Krishna1, J. Qian1, W. Hsu2, C. H. Chen3, Y. S. Cheng2, N. Tamarapalli4, W. T. Cheng4, J. Tofte4, M. Keim4, (1)Cisco Systems Inc, San Jose, CA, (2)Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan, (3)National Taiwan University, Taipei, Taiwan, (4)Mentor Graphics, Wilsonville, OR
In this paper we present a case study of yield learning for a 130nm device with 1 Million logic gates. Significant fallout was observed for a particular test pattern in the production stuck-at test pattern set. Adaptive ATPG, layout-aware scan diagnosis, and layout analysis were used to narrow down the suspected defect site. Physical failure analysis revealed a systematic bridge defect caused by metal residue left over because of dishing caused by CMP of underlying metal layers. Increasing the polishing resulted in restoring the yield back to the anticipated levels. Furthermore a new rule was added to the deck of bridge extraction rules such that, tests can be targeted to increase the quality of the outgoing parts, and diagnosis has the extra information to isolate the defects.
Defect Localization Technique for Logic Circuits in Sub 90nm SOI Microprocessors
T. Kane, M. P. Tenney, J. Bruley, S. Boettcher, IBM, Hopewell Junction, NY
Defect localization technique for isolating voltage, frequency and temperature sensitive logic circuits in sub 90nm SOI microprocessors.This technique overcomes limitations of logic chain diagnostics in terms of resolving to discrete circuit for subsequent failure analysis. This technique permits yield enhancement learning for voltage, frequency and temperature sensitive logic failures.
NBTI Reliability of Strained SOI MOSFETs
G. Thareja1, A. V. Y. Thean2, J. Lee1, V. Vartanian2, B. Y. Nguyen2, F. Zhu1, (1)University of Texas at Austin, Austin, TX, (2)Freescale Semiconductor Inc., Austin, TX
We investigated the degradation of device reliability due to Negative Bias Temperature Instability (NBTI) of PMOSFET on Strained Silicon on Insulator (S-SOI) substrates for the first time. The degradation has been found to be significantly higher for the S-SOI devices in comparison to SOI counterparts. Subsequent to a Constant Voltage Stress (CVS) during NBTI measurements, a negligible change in the subthreshold swing values has been observed. Thus it is believed that generation of fixed charge is responsible for the observed BTI shift in Threshold voltage (VTH) and transconductance (GM). Also higher BTI degradation was recorded for short channel devices.
Soft Defect Localization Technique for Design and Debug on DRAM Devices
M. Versen1, D. Diaconescu2, J. Touzel2, (1)University of Applied Sciences Rosenheim, Rosenheim, Germany, (2)Infineon Technologies AG, Munich, Germany
The SDL technique is applied to a DRAM device. The measurand is not a tester signal but an analogue DUT signal (a DQ signal). Pattern engineering and preparing experiments ensure that the signal is useful and measurable. Global heating experiments are conducted and the heating effect can be observed on the oscilloscope. Local heating is realised by an IR laser scanning microscope which provide also the imaging system. The experiments are done at 100MHz and we were able to localize two transistors in a sense amplifier that cause temperature dependent pass/fail behaviour. Internal voltage measurements show that the gate voltage of these transistors is not on target which is also the reason for the temperature dependent pass/fail behaviour.
Application of LADA for Post-Silicon Test Content and Diagnostic Tool Validation
C. L. Kong, Intel Corporation, Santa Clara, CA
A non-destructive methodology using laser assisted device alteration on state elements, such as static memory cell and scan latch structures, to validate and debug test content and tester diagnostic tools on working silicon.
Voltage Noise and Jitter Measurement Using Time-Resolved Emission
S. Kasapi1, G. L. Woods2, (1)NVIDIA, Santa Clara, CA, (2)Rice University, Houston, TX
Jitter measurements are increasingly important, especially in PLL-driven circuits and in high-speed serial links. In this paper we demonstrate completely non-invasive measurement of deterministic jitter inside an operating chip using time-resolved emission.
The Techniques for Short Failure Isolation on Advanced Technology
H. N. Lin, C. H. Wang, .. K. .. L. Lin, W. S. Yang, .. C. J. Chen, Taiwan Semiconductor Manufacturing Company Ltd, Kaohsiung County, Taiwan
OBIRCH (Optical Beam Induce Resistance Change) is one popular method for isolating short failures for process development test structures on 130nm and 110nm technology. As technology progresses and the width of metal line shrinks, we still apply this method for the failure analysis of 90nm metal line. However, we have some issues for OBIRCH inspection on 90nm technology. The OBIRCH signals of samples were so weak, even nothing or just noise. It becomes so difficult to locate the defect by OBIRCH. The weak OBIRCH signal is caused by the shrinking in metal line and metal spacing which induce the increase of resistance. We found two solutions for isolating the failure. The first method is to calculate the position of defect by electrical measurement; the second method is to enhance the OBIRCH signal for accurately localizing defect using circuit modification. These two methods can successfully locate the defect, and help us to improve the efficiency of physical failure analysis. The paper will demonstrate the details of these two techniques.
Buttons and Threads: Tailoring Defect Analysis
C. F. H. Gondran1, D. F. Paul2, S. K. Das3, B. Foran1, M. H. Clark1, (1)ATDF at International SEMATECH, Austin, TX, (2)Physical Electronics, Chanhassen, MN, (3)IBM Assignee to SEMATECH, Austin, TX
This work presents a quick check for considering the geometry of a specific defect when selecting AES or STEM-EELS as an analytical technique. The approach is derived from basic geometric considerations and illustrated with a case study: a comparison of STEM-EELS and AES analysis of ~ 10-20 nm particle defects found on a dense line structure.
Marginal Deviation of Thermal Budget Bring Shallow Junction Formation Failure Forth Study
T. C. Chuang1, C. M. Shen2, J. H. Chou1, (1)Taiwan Semiconductor Manufacture Company, Ltd., Tainan, Taiwan, (2)Taiwan Semiconductor Manufacture Company, Ltd., Taiwan, Hsin-Chu, Taiwan
According to our research, the thermal budget induced abnormal dopant distribution and lower concentration per centimeter third were revealed and feedback to Fab. The flash lamp annealing failure mode has been improved since then. No similar faulty has been observed thereafter.
Metal Slice Defect Induced Package Level Reliability Failure
M. Zhang1, S. Liao2, S. Liang3, R. Lou4, R. Chen2, C. Niou3, K. Chien2, (1)Semiconductor Manufacturing International Corperation, Shanghai, China, (2)Semicoductor Manufacturing International Co., Shanghai, China, (3)Semiconductor Manufacturing International (Beijing) Corp, Beijing, China, (4)Semiconductor Manufacturing International Corporation(SMIC), Shang Hai, China
In this paper, one package level reliability test failure analysis case was studied, and some experiments were done to get the root cause. From the result, one model of “Slice defect” is proposed, and multiple experiment data are shown as evidences to confirm the result.
Vanishing TiN ARC Coating as an Indicator of EOS in Aluminum Top Metal Lines
T. J. Barbieri1, J. Wang1, M. Kottke1, D. Theodore1, R. Wetz2, (1)Freescale Semiconductor, Inc., Tempe, AZ, (2)Tyco Healthcare, Boulder, CO
In the analysis described in this paper, multiple parts failed during a 96 hour HAST (highly accelerated stress test) run. FA of the failed parts identified an indirect method of identifying low-grade electrical overstress (EOS) on thin, top-layer aluminum metal lines with TiN anti-reflective coating (ARC). Visual inspection suggested that passivation and ARC had been removed from several top-metal lines due to their optical appearance. SEM inspection found that this was not true. Passivation was observed to be intact, but cracked. A series of experiments utilizing FIB cross-sections, Auger mapping, Auger depth profiling, TEM inspection and EDS were used to show that the TiN had not been removed; it had, in fact, been oxidized, which resulted in the change of appearance.
Accelerated Corrosion of Printed Circuit Boards Due to High Levels of Reduced Sulfur Gasses in Industrial Environments
P. Mazurkiewicz, Hewlett-Packard Corporation, Fort Collins, CO
Accelerated corrosion leading to system failure has been observed on printed circuit boards present in industrial environments that contain abnormal levels of reduced sulfur gasses, such as hydrogen sulfide (H2S) and elemental sulfur.
Fine MCP Decapsulation Technology Development
J. Zhou, W. Zheng, T. Lee, Samsung Semiconductor China R&D Co. Ltd., Suzhou, Jiangsu Province, China
A new MCP decapsulation technology combining mechanical polishing with chemical etching is introduced. This new technology can remove the upper die quickly without damaging the bottom die due to using KOH and TMAH. The technology application and relative process are presented. The factors that affect the KOH and TMAH etching speed are studied. The difference between KOH etching and TMAH etching is discussed.
Correlation Study of Delamination Gap Detection Capability of SAM and Cross Section/SEM Analysis
J. C. P. McKeon1, S. L. Tan2, H. S. Jang3, (1)Sonix Inc., Springfield, VA, (2)Texas Instruments Malaysia Sdn Bhd, Kuala Lumpur, Malaysia, (3)Sonix Inc., Seoul, South Korea
This paper will discuss the delamination detection capability of SAM and cross sectioning / SEM for encapsulated packages. The techniques required and limitations of each tool will also be discussed.
Measurement Techniques for Thermally Induced Warpage to Predict Ball Grid Array Package-on-Package Solder Compatibility
T. B. Davis, T. Krawzak, M. Morrison, J. Reeder, T. Jiang, Micron Technology, Boise, ID
Discusses sample preperation, warpage measurement, data colletion, and mathmatical usage of data to determine solderability for package on package ball grid array parts.
Atomic Force Probe Kelvin Measurements of Large MOSFET Devices at Contact Level for Accurate Device Threshold Characteristics
T. Kane1, M. P. Tenney1, A. N. Erickson2, S. Phan2, (1)IBM, Hopewell Junction, NY, (2)Multiprobe, Inc, Santa Barbara, CA
Large Gate width devices associated with peripheral SRAM logic circuits, PLL analog circuits, and Analog current mirrors places challenges reconstruction of threshold measurements at contact level.Kelvin measurments by Atomic Force Probing with a novel probe placement is essential for valid device threshold measurements such as Vtsat, Vtlin.
Atomic Force Probe Analysis of Non-Visible Defects in Sub-100nm CMOS Technologies
R. E. Mulder1, S. Subramanian2, T. Chrastecky2, (1)Silicon Labs, Austin, TX, (2)Freescale Semiconductor, Inc., Austin, TX
As the minimum feature lengths for CMOS technology devices continue to shrink well below the sub-100nm threshold, the physical defects that cause device failure are also decreasing in size. The gate oxide thickness for sub-100nm technologies is typically 10-20A which is equivalent to a few mono-layers of SiO2 atoms. The smallest defect or processing anomaly in these thin gate oxides can cause a significant increase in the gate leakage resulting in device failure. Also, very subtle substrate problems in regards to doping, lattice structure defects and processing can also cause device failure. These types of defects and processing problems in sub-100nm technologies have basically become invisible to the tools that worked well to image and identify gate oxide and substrate problems in older technologies such as the Scanning Election Microscope(SEM) and Transmission Electron Microscope(TEM). Instead, these failure mechanisms will have to be identified through the electrical characterization of the failing transistor. Fortunately for the failure analysis community, the probing and electrical analysis of individual failing transistors at the sub-100nm technology level can now be performed with Scanning Probe Microscopy (SPM) technology or specifically Atomic Force Probing. This paper will demonstrate how Atomic Force Probing can be used to carefully characterize failing transistors and identify failure mechanisms to allow device/process engineers to make adjustments to the wafer fabrication process to correct the problem even if physical analysis with SEM/TEM is not able to image and identify a defect.
90nm Technology SRAM Soft Fail Analysis Using Nanoprobing and Junction Stain TEM
G. Zimmermann1, S. Mueller2, (1)Infineon Technologies Taiwan Co., Ltd., Hsinchu City, Taiwan, (2)Infineon Technologies AG, Munich, Germany
This article describes a 90nm technology SRAM soft fail analysis. Affected wafers show a large number of wafer edge dies failing for single cell cluster fails at voltages below 1.0V. The cluster fails appear in characteristic areas within a 512k dualport SRAM memory block, but do not affect the edge of the memory block. Nanoprobing was used for electrical localization at cell level by means of a Zyvex system inside a SEM and a Multiprobe AFP system. Measurements of an identical fail sample are in good agreement for both systems. We will also briefly discuss the advantages of both systems. The fail area exhibits very weak PFET IV characteristics, while the drain currents of NFET cell transistors are in the expected range. For fail visualization a junction stain was applied to a TEM lamella to delineate areas with different doping levels. Due to the difference in etch behavior of the fail and a reference area, a partially blocked source/drain (S/D) implant was identified for causing the fail.
Nano-Probing Application on Characterization of 6T-SRAM Single Bit Failures with Different Gox Breakdown Defect
Y. L. Kuo1, C. H. Wu2, C. P. Lin2, C. H. Tang2, C. C. Ting2, (1)Taiwan Semiconductor Manufacturing Company, Ltd., Taiwain, China, (2)Taiwan Semiconductor Manufacturing Co., Hsin-Chu, Taiwan
In this paper, real SRAM failures were analyzed by using nano-probing system. The correlation between electrical symptoms of discrete 6T-SRAM cells with SBD and failure mode is clearly revealed
In Situ Electron Microscopy Study of Current-Induced Failure of Carbon Nanofibers
M. Suzuki1, Y. Ominami2, Q. Ngo2, K. J. McIlwrath3, K. Jarausch3, A. M. Cassell4, J. Li5, C. Y. Yang2, (1)SaHitachi High Technology Corporationnta Clara University, Santa Clara, CA, (2)Santa Clara University, Santa Clara, CA, (3)Hitachi High Technologies America, Pleasanton, CA, (4)NASA Ames Research Center, Moffett Field, CA, (5)Semprus BioSciences, Cambridge, MA
Carbon nanotubes (CNTs) and carbon nanofibers (CNFs) are possible candidates for the next-generation interconnect materials for VLSI circuits. We performed an in situ electron microscopy study of CNF failure due to high-current stress. The breakdown along the side of the cup-shaped graphitic layer was observed. The results suggest that optimization of the layer structure of CNF is the key to higher current capability.
Near-Field Scanning Microwave Probe for Rapid Detection of Non-Visual and Parametric Defects in Cu/Low-K Interconnect on Production Wafers
V. V. Talanov, A. R. Schwartz, Neocera, Inc., Beltsville, MD
We demonstrate the use of a near-field scanned microwave probe (NSMP) for FA of parametric defects in Cu/low-k interconnect that leave no physical remnant (sometimes referred to as “non-visual defects”). This technique is rapid, quantitative, non-contact, and provides direct electrical measurements. The area required for the measurement is as small as 30x30 micron, easily fitting into the scribe line on production wafers.
Non-Invasive Acoustic Phonon Characterization of Dynamic MEMS
W. K. Wong, M. Palaniapan, C. L. Wong, S. Wang, F. E. Tay, National University of Singapore, Singapore, Singapore
This paper describes an acoustic phonon-based characterization technique as a novel alternative tool for the characterization of dynamic microelectromechanical (MEMS) devices such as MEMS resonators, switches, micromirrors, accelerometers and gyroscopes. The technique intrinsically features high throughput and non-invasive characterization due to the favorable transmission properties of acoustic phonons through solids, which facilitates high volume wafer and package level testing. The dependence of phonon generation on material properties yields information not commonly obtained in existing electrical, optical and electron beam testing techniques such as contact tribology, energy dissipation, non-linear device response and device resonance modes. Present case study results show that phonon-based characterization not only provides efficient, non-destructive testing (NDT) of basic MEMS functionality but also insights into MEMS device lifecycle behavior.
Magnetic Current Imaging with Magnetic Tunnel Junction Sensors: Case Study and Analysis
B. D. Schrag, M. J. Carter, X. Liu, J. S. Hoftun, G. Xiao, Micro Magnetics, Inc., Fall River, MA
We present an in-depth discussion of the use of magnetic tunnel junction sensors to map currents for fault isolation in semiconductor die. First, a full case study is presented, in which faults are isolated in a new ASIC using magnetic current imaging with a scanning magnetic tunnel junction sensor probe. We also discuss the sensitivity and spatial resolution of magnetic tunnel junction sensors as compared with giant magnetoresistive sensors.
Analysis and Identification of Off Odor Compounds in Electronic Systems
M. A. Nailos1, D. Stein1, L. T. Nielsen2, A. Iwasinska2, (1)Dell, Inc., Round Rock, TX, (2)Microanalytics, a MOCON Company, Round Rock, TX
Identification of odor causing compounds using a specifically-designed-for odor analysis system. The example used in the paper is an off odor on a stamped metal part. The suspected source is a trace level contaminant in a stamping oil used in its manufacture.
System Failure Analysis Process and Case Study
N. Konkol, Intel Corporation, Hillsboro, OR
This abstract is concerning a case study of using system level debug techniques for PC mother boards.
Using a Unified Data Stream to Drive Failure Analysis for Product Improvement in the Personal Computer (PC) Environment
S. J. Horley1, J. Rascon2, (1)Intel Corporation, Hillsboro, OR, (2)Intel Corporation, Chandler, AZ
The longer defective units are in the manufacturing pipeline before they are detected, the more expensive it becomes. Therefore, economic pressures drive the requirement to capture failures and perform root cause analysis further upstream in the product manufacturing cycle. This places greater emphasis in the ability to identify failures and perform value add analysis to drive product improvements as early as possible. The topic of discussion will be the method used to develop a reliable Unified Data Stream (UDS) that feeds the failure analysis process which in turn provides actionable information to product development teams in the Personal Computer (PC) environment.
Triangulating to a Defect's Physical Coordinates Using Multiple Supply Pad IDDQs: Test Chip Results
J. Plusquellic1, D. Acharyya2, M. Tehranipoor2, C. Patel2, (1)University of Maryland Baltimore County, Baltimore, MD, (2)University of Maryland Baltimore County, NA, MD
Quiescent Signal Analysis (QSA) is an IDDQ method for detecting defects that is based on the analysis of multiple simultaneous measurements of supply port IDDQs. The nature of the information in the multiple IDDQs measurements also allows for the localization of the defect to physical coordinates in the chip. In previous work, we derived a hyperbola-based method from simulation experiments that is able to "triangulate" the position of the defect in the layout. In this paper, we evaluate the accuracy of this method using data collected from 12 chips fabricated in a 65 nm process.
Logical-to-Physical Device Navigation Using Place-and-Route Data as an Alternative to LVS
R. A. Nicholson, Credence Systems Corporation, Milpitas, CA
Logical-to-physical device navigation for failure analysis is often used to drive physical probers and focused ion beam tools. Traditional methods of creating navigation data rely upon the use of time consuming LVS-based methods. By using existing place-and-route data, full cross-linked navigation between schematic and physical layout may be achieved in a fraction of the time that it takes for the LVS methods to be used. Place-and-route data offers significantly more information to the analyst than LVS based data.
Fundamental Considerations for CDM Failure in 90nm Products
N. Wakai, Y. Kobira, Toshiba Corporation, Yokohama, Japan
Fundamental consideration for CDM breakdown was investigated with 90nm technology products and others. According to the result of failure analysis, it was found that gate oxide breakdown was critical failure mode for CDM test. High trigger speed protection device such as ggNMOS and SCR is effective method to improve its CDM breakdown voltage and an improvement for evaluated products were confirmed. However, it is expected that CDM protection designing will be in severer situation because of technology development. Down-scaling of protection device size makes technologies vulnerable and huge number IC pins of high function package gives severer CDM stress. In order to solve these problems in the product, fundamental evaluations were performed. Those are a measurement of discharge parameter and stress time dependence of CDM breakdown voltage. Peak intensity and rise time of discharge current as critical parameters are well correlated their package capacitance. Increasing stress time causes breakdown voltage decreasing. This mechanism is similar to that of TDDB for gate oxide breakdown. Results from experiences and considerations for future CDM reliable designing are explained in this report.
Development of a Circuit Edit Process Scalable in Dimension and Material
V. V. Makarov1, N. Antoniou2, (1)Tiza Lab, LLC, Milpitas, CA, (2)Credence Systems Corp., Sunnyvale, CA
The ability to edit circuitry in silicon quickly and confidently is extremely valuable as it permits verification of design changes or fixes without the need to generate new reticles and fabricate new silicon. The ability to extend this capability into the future requires the development of circuit edit (CE) processes that scale with the semiconductor technology and are material independent.
Quantitative Electrical Analysis of FIB Prepared Vias on BiCMOS and CMOS090 Designs
B. Domenges1, P. Poirier2, (1)CNRT-CNRS, caen, France, (2)Philips Semiconductors, CAEN, France
In this study, the resistance of FIB prepared vias was characterized by Kelvin probe technique and its evolution studied versus the section of the vias. Two domains of resistivity were isolated in relation to the ion beam current used for the deposition of the Pt. Also sub-micrometer vias were investigated on 4.2µm deep metal lines of BiCMOS aluminum based design and CMOS 090 copper based one. It is shown that the main parameter is the true section of the contact, the latter being favored by an adequate drill of the via inside the metal line
Study on the Effect of FIB Electron Beam Assisted Platinum Deposition on TEM Sample Analysis
J. Hu1, J. Zhou2, M. Li3, Q. Gao4, C. Niou5, K. Chien3, (1)Semiconductor Manufacturing International Company, Shanghai, China, (2)Semiconductor manufacturing international Company, Shanghai, China, (3)Semicoductor Manufacturing International Co., Shanghai, China, (4)Semiconductor Manufacturing International Corporation, Shanghai, China, (5)Semiconductor Manufacturing International (Beijing) Corp, Beijing, China
As the electron beam assisted Pt deposition brings almost no damage to the sample surface during FIB (focused ion beam) sample treatment, it became a very effective way to protect the sample surface from being damaged. In this paper phenomenon related to electron beam assisted deposition of platinum were studied. It showed that a 45 nm thick remain E beam Pt could effectively protect (100) silicon from damage induced by ion beam assisted Pt deposition (with extract voltage of 30 KV, current of 30 pA, etc). Also carbon based organic layer under electron beam assisted Pt was observed. Its mechanism and influence on exposed oxide thickness measurement was discussed. It is suggested carbon glue cap as the protective layer or poly silicon deposit in line before the wafer submitting for TEM observation.
Experiment Study on Crystal/Amorphous Structure of TEM Samples Prepared by FIB Milling
Q. Gao1, M. Zhang2, C. Niou3, M. Li4, W. T. K. Chien5, X. Chen6, (1)Semiconductor Manufacturing International Corporation, Shanghai, China, (2)Semiconductor Manufacturing International Corperation, Shanghai, China, (3)Semiconductor Manufacturing International (Beijing) Corp, Beijing, China, (4)Semicoductor Manufacturing International Co., Shanghai, China, (5)Semiconductor Manufacturing International Company, Shanghai, China, (6)Semiconductor Manufacturing International (Shanghai) Corp, Shanghai, China
Single crystal silicon TEM sample structure was studied experimentally. A novel sample and its fabrication process were reported in this paper. The sandwich structure can be observed directly in TEM with this sample, which was never reported before. When the crystal layer in monocrystal silicon is less than 18 nanometers, the sample will be observed as full amorphous.
Advanced Fringe Analysis Techniques in Circuit Edit
R. K. Jain1, T. Malik1, T. Lundquist1, C. C. Tsao1, W. Walecki2, (1)Credence Systems Corporation, Sunnyvale, CA, (2)Frontier Semiconductor, Inc, San Jose, CA
Advanced Fringe analysis techniques in circuit edit are discussed using a coaxial photon-ion column. Emphasis is put on accurate end point detection and maintaining co-planarity in new technology circuit edit for higher success rate.
Direct Measurements of Charge in Floating Gate Transistor Channels of Flash Memories Using Scanning Capacitance Microscopy
C. De Nardi1, R. Desplats2, P. Perdu2, C. Guérin3, J. L. Gauffier4, T. B. Amundsen4, (1)CNES-French Space Agency, Toulouse, France, (2)CNES - French Space Agency, Toulouse, France, (3)DGA/CELAR French Defense Department, Bruz, France, (4)Institut National des Sciences Aplliquées (INSA), Toulouse, France
Failure Analysis have to deal with challenging questions about stored charges in floating gates in Non Volatile Memories (NVM) when reading does not give expected data. Access to this information will help to understand failure mechanisms. A method to measure on-site programmed charges in Flash EEPROM devices is presented. Scanning Capacitance Microscopy (SCM) is used to directly probe the carrier concentration on Floating Gate Transistor (FGT) channels. The methodology permits to map channels and active regions from the die backside. Transistor charged values (ON/OFF) are measured and localized with a 15 nm resolution. Both preparation and probing methods are discussed. Applications are demonstrated on two different Flash technologies: the two-transistor cell (2T-cell) from Atmel and the one-transistor cell (1T-cell) from STMicroelectronics.
Development of Backside Scanning Capacitance Microscopy Technique for Advanced SOI Microprocessors
V. Narang1, P. Muthu1, J. Chin2, V. Lim3, (1)AMD Singapore, Singapore, Singapore, (2)Advanced Micro Devices Pte Ltd, SIngapore, Singapore, (3)Institute of Microelectronics,, Singapore, Singapore
Implant related issues are hard to detect with conventional techniques for advanced devices manufactured with deep sub-micron technology. This has led to introduction of site-specific analysis techniques. This paper presents the scanning capacitance microscopy (SCM) technique developed from backside of SOI microprocessor devices for packaged products. The challenge from backside method includes sample preparation methodology to obtain a thin high qualityoxide layer, SCM parameters optimization, data interpretation and establishing repeatability. Optimization of plasma etching of buried oxide followed by a new method of growing thin oxide using UV/ozone is also presented. This oxidation method overcomes the limitations imposed due to packaged unit not being able to heat to high temperature for growing thermal oxide. Backside SCM successfully profiled both the n and p type of dopants in both dense and isolated transistors.
Material and Doping contrast in Semiconductor Devices at Nanoscale Resolution Using Scattering-Type Scanning Near-Field Optical Microscopy
J. Wittborn1, D. V. Kazantsev2, A. Huber2, R. Weiland1, F. Keilmann2, R. Hillenbrand2, (1)Infineon Technologies AG, Munich, Germany, (2)Max-Planck-Institut für Biochemie, Martinsried, Germany
We demonstrate that scattering-type near-field optical microscopy (s-SNOM) operating at mid infrared wavelengths, λ = 10 μm, can be applied for nanoscale resolved mapping of material and doping in cross-sectional samples of microelectronic circuits.
Identification of Root Cause Failure in Silicon on Insulator Body Contacted nFETs Using Scanning Capacitance Microscopy and Scanning Spreading Resistance Microscopy
J. McMurray, C. M. Molella, IBM Microelectronics, Hopewell Junction, NY
A new sample preparation was created to allow plan view samples to be created for the acitve silicon - buried oxide interface. This new preparation technique allowed a low carrier region in failing body contacted nFETs to be identified.
Intermittent Failures in High Pin Count Packaging
R. Varma1, C. Messick2, R. Brooks1, R. Twist1, J. Arnold1, (1)Northrop Grumman Corporation, Linthicum, MD, (2)Northrop Grumman Corporation, Clearfield, UT
Qualification testing must include decapsulation and wire pull before declaring a part reliable. Fuming Nitric can be used to decapsulate the part, but care must be taken to expose the same amount of wire as measured from the bond pad. FIB, Auger and intermittent testing analysis are useful in verifying wire pull failures.
Microstructure Analysis of Wafer Bump Nodule
X. Chen1, T. Ge2, L. Tsou2, M. Li3, C. Niou4, W. T. K. Chien3, (1)Semiconductor Manufacturing International (Shanghai) Corp, Shanghai, China, (2)Semiconductor Manufacturing International Corp., Shanghai, China, (3)Semicoductor Manufacturing International Co., Shanghai, China, (4)Semiconductor Manufacturing International (Beijing) Corp, Beijing, China
In this work, wafer bump growth mechanism was discussed. And microstructure of wafer bump nodule was analyzed by FIB, SEM and EDS.Solution of preventing wafer bump nodule growth was advanced.
Packaging Material has Contributed to High Idd_Pd Failures in CMOS ICs
M. C. Pun, G. E. Chew, N. Sulaiman, Avago Technologies (M) Sdn. Bhd., Penang, Malaysia
A New Methodology for Electrical Debugging Short in Packages with Modified Daisy-Chain Die
C. McMahon1, S. K. Hsiung2, K. V. Tan2, J. Soopikian2, (1)LSI, Fort Collins, CO, (2)LSI Logic Corporation, Fremont, CA
In this paper, a new methodology that combines Resistance Analysis, TDR Isolation and SSM Identification for electrical debugging short in packages with modified daisy-chain die will be presented. Case studies will also be discussed.
Inductive Operation Life Stress Metal Breakdown Mechanism
B. T. Gillette, Fairchild Semiconductor Corp, Mountaintop, PA
Inductive Life Stress devices in a deteriorated state were encountered at the 168 hour read during experimental testing. A metal grain boundary breakdown mechanism was found during the analysis of the device, which was creating a gross electrical short gate to source and gate to drain. The AlSiCu top metal was breaking down along the grain boundaries. There was alloying of the source Al bondwire into the substrate. This alloying was creating a short to the gate, source, and drain. Several variations in the metal stack and testing conditions were evaluated to better understand the cause of the devices inability to with stand Inductive Life stress and to provide a process solution. The prevention of the AlSiCu top metal grain boundary breakdown during inductive life stress testing required a die size and testing condition change. This change resulted in a reduced grain boundary breakdown and consequently prevented Al grain boundary breakdown, TiW barrier breakdown and Al spiking induced metal breakdown mechanism. The die change and modified testing conditions resulted in a successful pass through the inductive life stress testing.
Root Cause Finding of a Diode Leakage Failure using Scanning Magnetic Microscopy and ToF-SIMS as Key Methods
H. Preu1, W. Mack1, T. Kilger1, B. Seidl1, P. Alpern2, M. Kirchberger1, (1)Infineon Technologies AG, Regensburg, Germany, (2)Infineon Technologies AG, Neubiberg, Germany
In this case study we present a successful approach for failure analysis of a diode leakage. An analytical flow will be introduced, which contains standard techniques as well as SQUID (superconducting quantum interference device) scanning magnetic microscopy and ToF-SIMS as key methods for localization and root cause identification.
Temperature and Humidity Dependent Reliability Analysis of RGB LED Chip
J. Fu1, S. Souri1, J. Harris2, (1)Exponent Failure Analysis Associates, Inc, Menlo Park, CA, (2)Stanford University, Stanford, CA
An intermittent failure mode of surface-mounted RGB LED chips was identified due to the delamination resulting from the inappropriate PCB reflow process. Temperature and humidity dependent reliability analysis was performed based on the junction temperature measurements derived from the emission spectra and the junction voltage, respectively.
A Study of Low Leakage Failure Mechanism of X7R Multiple Layer Ceramic Capacitor (MLCC)
Z. Wang, International Rectifier, Temecula, CA
Failure mechanism study on latent failure of BaTiO3 capacitors that have low leakage (in the tens of uA), no crack nor any other gross defect.
A System for Electro-Mechanical Reliability Testing of MEMS Devices
S. Spinner, M. Doelle, P. Ruther, I. Polian, O. Paul, B. Becker, University of Freiburg, Freiburg, Germany
We report an experimental test system which enables the automated analysis of mechanical stress impact on the reliability of microelectromechanical systems (MEMS). With this system, in-situ electrical characterization and optical inspection are performed while subjecting MEMS devices to defined mechanical loads. Impact objects of various geometries, e.g., contact probes or wafer prober needles, can be applied which are aligned relative to the MEMS device using an xyz-nanopositioning stage with a positioning accuracy of 20 nm. This positioning stage enables programmable static forces up to 3.6 N and dynamic loads at frequencies up to 20 Hz. With this highly flexible system reliability tests, postmanufacturing tests and stress screens can be performed on single chips as well as on whole wafers with diameters up to 6 inch. Preliminary results on long-term reliability tests using CMOS-based stress sensors exploiting the piezoresistive effect in field effect transistors are presented.
CMOS Electronics and Defect Analysis
C. Hawkins, University of New Mexico, Albuquerque, NM
This is a review of CMOS electronic theory that applies to failures, is followed by a description of the behaviors of open and bridging defects. These behaviors depend mostly on defect location and size of the defect. Parametric failures are a third class of failure with entirely different properties. These failures are very dependent on environmental conditions (VDD, temperature, clock frequency) and interdie statistical variation.
Flash Memory Failure Analysis
R. R. Mitchell, Intel, Folsom, CA
Flash memories have become the dominant non-volatile memory solution for many low power mobile devices. This tutorial will provide an introduction to failure analysis as it relates to flash memory technology. Topics that will be addressed include: NOR flash cell architecture, flash cell physics, customer usage models, reliability issues, and applicable failure analysis tools and techniques. The focus of this presentation will be on flash memory failure modes and the techniques and equipment that are used to isolate failures.
Failure Analysis of DRAM Memory
M. Versen, University of Applied Sciences Rosenheim, Rosenheim, Germany
Failure analysis of DRAMs requires an understanding of the functional operation and specific fail behaviors. This tutorial explains how electrical failure analysis establishes the basis for a successful physical failure analysis. An introduction to the memory operation is given with a focus on the device response to external commands. Some failure analysis examples for the memory array are presented relating to read and write failures.
Failure Analysis of SRAM Memory
S. Gunturi, Texas Instruments, Inc., Dallas, TX
Failure analysis of SRAM memory requires the understanding of the components of cell, the operation of SRAM, layout, testing and the electrical signature of the fails. An overview of all the above aspects will be provided as an introduction. The methodology of failure analysis of SRAM is described showing the interaction of SRAM testing, electrical failure signature and the probable cause of fail, which can lead to physical failure analysis.
*NEW FOR 2006* Emerging Technologies for IC Fabrication in 2006
S. Wolf, Lattice Press, TBD, CA
CMOS IC Technology has progressed for over 40 years primarily by laterally shrinking the MOSFET feature sizes and the gate-dielectric thickness (“scaling). As the 45-nm CMOS technology node is approaching, such “classical” scaling is reaching its limits. New process technologies and materials are needed to allow the 45-nm CMOS (and beyond) to be reached. In this tutorial, we will briefly survey these emerging technologies, including: Strained silicon: Hi-k gate-dielectrics; Metal gate-electrodes; Ultra-shallow S/D junctions; Atomic-layer deposition (ALD); Dual-damascene Cu/Low-k Interconnects; Advanced Lithography; Silicon-on- Insulator, and “Non-classical” IC devices.
*NEW FOR 2006* Emerging Trends in Failure Modes of Nanotechnology
T. Kane, IBM, Hopewell Junction, NY
The evolution in Moore's Law means a shift away from processor performance to system performance. To achieve improved system performance, novel materials such as back end of line low-k dielectric materials, thinner gate oxide films and/or high-k gate dielectric films must be implemented. These materials represent challenges to conventional failure analysis involving new failure modes.
In addition, strain induced device enhancements for PMOS and NMOS devices already implemented at 90 nanometer node with improved electron mobilities and hole mobilities can introduce new failure modes.
To achieve requisite system performance for sub 45 nanometer nodes, novel structures such as two dimensional FINFET designs will be required challenging conventional failure analysis localization and analysis.
How Transmission Line Pulse (TLP) ESD Testing is used for ESD Failure Analysis
L. G. Henry, ESD-TLP Consulting & Testing, Fremont,, CA
For over 26 years, ESD Testing methods have been used to determine the different ESD failure threshold levels of electronic components. There are four ESD Testing Methods from the four ESD events, namely the Human Body Model (HBM), the Machine Model (MM), the charged Device Model (CDM) and the Human Metal Model (HMM). The first three methods are normally used for the qualification of ICs before they are shipped, and the fourth is used to qualify systems before they are shipped to the European market.
Over the last 16 years, researchers have used an additional (5th) ESD testing method to characterize the ESD protection structures of these electronic components. This 5th method, the Transmission Line Pulse (TLP) ESD method, is regarded as a diagnostic tool, and so it was used for engineering evaluation and development with a goal to improving the robustness of the ESD protective structures in ICs.
The practical basis and basics of TLP will be discussed and the failure criteria will be linked to the failure criteria of the traditional HBM ESD testing. The TLP pulse parameters and testing results will be compared with that from the traditional HBM in order to show that correlation exists between the two methods of ESD Testing. Examples of TLP test results from case studies, including the subsequent failure analysis, will be presented.
Electrical Overstress (EOS) in Semiconductor Devices: How to Differentiate and Document EOS due to Over-Current or Over-Voltage Conditions
C. Lewis, Texas Instruments, Dallas, TX
Electrical Overstress (EOS) in its various incarnations is a constant cause of failure for integrated circuits. As circuit geometries shrink and with it a decrease in operating voltages; devices are more susceptible to EOS failure due to over-voltage or/and over-current transients. This is particularly true when devices are assembled into end-item customer board assemblies and are subjected to system level stresses. Discussions with end-item customers reveal that just reporting EOS is no longer acceptable. The purpose of this presentation is to understand the causes of EOS and ESD and understand the impact on semiconductor devices. Due to the challenge of differentiating EOS and ESD, we propose a flowchart that will, first establish a foundation of data collection for all types of failure modes. And secondly, establish appropriate data collecting protocols for verified EOS/ESD stressed devices.
Failure Analysis Process Basics
V. Chowdhury, Altera Corp., San Jose, CA
This tutorial emphasizes the importance of a methodical approach to failure analysis through a development of failure models during the electrical debug process and an effective use of the defect analysis tools. The tutorial wil go over some case studies to emphasize on an understanding of the tools and how to exploit them to achieve the results during the debug process. The tutorial will also touch on the need for novel techniques in view of the shrinking/changing processes and materials.
Classic Case Histories
J. Colvin, FA Instruments, San Jose, CA
Understanding the electrical failure signature is paramount to effective failure analysis. Defect localization techniques like (Photoemission, IR, OBIRCH/TIVA, SIFT, etc.) are excellent tools of choice, however, the analyst must understand when and which of these techniques are applicable. The classic case studies compiled in this tutorial are based on the tools, techniques and the philosophy of analysis utilized in each case study. We will discuss a scenario where several test tools and strategies are utilized to localize the failure before physical failure analysis is carried out.
Delayering Techniques: Dry Processes, Wet Chemical, Parallel Lapping
K. S. Wills1, S. Perungulam2, (1)Independent Consultant, Sugar Land, TX, (2)Texas Instruments, Stafford,, TX
The ability to deprocess the semiconductor device without the introduction of artifacts related to the processing is critical to proper defect identification. Presented here will be the advantages and limitations of wet deprocessing. Techniques such as delayering using wet chemicals for metals (including Al, Cu), dielectrics, barrier layers, and silicon will be discussed. Techniques for cross section staining will be presented along with techniques for location of defects in a silicon substrate.
Electromigration in Copper Interconnects - Degradation Studies and Failure Analysis
M. A. Meyer1, E. Langer2, H. J. Engelmann1, E. Zschech1, (1)AMD Saxony LLC & Co. KG, Dresden, Germany, (2)GLOBALFOUNDRIES, Dresden, Germany
Electromigration in copper interconnects is a prominent challenge for the introduction of new technologies and materials at constantly shrinking feature sizes. Physical failure analysis by means of FIB, SEM, and TEM, etc. are important methods to support reliability monitoring and process development. The tutorial focuses on SEM in situ degradation experiments of copper interconnects and failure analysis of post mortem EM test samples. A detailed description of methodology/experimental setup of the SEM in situ experiments as well as case studies for different technological approaches will be given. The use of FIB, SEM (EBSD), TEM (EDS) as well as other methods for physical failure analysis will discussed from an overview perspective.
Physics of Failure - The Good Part about Bad Parts
C. Bunis, M/A-COM Tyco Electronics, Lowell, MA
Determining the physics of failure after a controlled experiment or after a field failure is essential in understanding products and their limitations. Finding a root cause is beneficial to decrease repeat failures and set the specification limits on products. Using failure analysis along with understanding the basic materials science behind the product is vital in resolving problems and customer satisfaction. This Physics of Failure section will include the “why's” of failure, including diffusion, metal migration, corrosion, phase diagrams and solder properties.
Lock-in Thermography
O. Breitenstein1, F. Altmann2, T. Riediger2, D. Karg3, (1)Max Planck Institute of Microstructure Physics, Halle, Germany, (2)Fraunhofer Institute for Mechanics of Materials, Halle, Germany, (3)Thermosensorik GmbH, Erlangen, Germany
Microscopic infrared (IR) thermography has been used in steady-state mode for failure analysis since many years. However, its temperature resolution is limited to the order of 100 mK, and the emissivity contrast complicates the interpretation of results. In lock-in thermography (LIT), the power dissipation in the IC is periodically pulsed, the device is imaged by an IR microscope, and the incoming IR images are numerically processed and averaged on-line, according to the lock-in principle. After an averaging time of typically 30 minutes, T-modulation amplitudes below 100 µK are detectable. This reduces the detection limit for local heat sources, compared to traditional IR microscopy, by a factor of 100 and thus greatly expands the application field of LIT in failure analysis of ICs. Lock-in thermography with two phase detection allows to display images, which are inherently free of the emissivity contrast. By using a solid immersion lens, a spatial resolution of 1.5 µm may be obtained.
The Role of the Atomic Microscope in Failure and Yield Analysis
A. N. Erickson1, J. Colvin2, (1)Multiprobe, Inc, Santa Barbara, CA, (2)FA Instruments, San Jose, CA
The Scanning Probe Microscope (SPM) has become an indispensable tool for failure analysis and FAB process characterization. The SPM more commonly known as the Atomic Force Microscope (AFM) can do much more than just image a surface. Interest in SPM for FA is increasing due to new AFM technologies and broader exposure to semiconductor applications information, primarily from wafer process measurements. These technologies include scanning capacitance, thermal, current and voltage microscopies (SCM, STHM, EFM, SKPM, CAFM) as well as more recent availability of microscopes that allow access for measurements on operating, packaged devices.
Flip-Chip and Backside Analysis Techniques
E. I. Cole1, D. L. Barton2, K. Bernhard-Höfer3, (1)Sandia National laboratories, Albuquerque, NM, (2)Sandia National Laboratories, Albuquerque, NM, (3)Infineon, Munich, Germany
State-of-the-art techniques for failure localization and design modification through bulk silicon are essential for multi-level metallization and new flip chip packaging methods. This tutorial reviews the transmission of light through silicon, sample preparation and highlights several backside defect localization techniques that are both currently available and under development. The techniques covered include emission microscopy, scanning laser microscope based techniques (electro-optic techniques, LIVA and its derivatives) and other non-IR based tools (FIB, e-beam techniques, etc.).
Photonic Localization Techniques
C. Boit, TUB Berlin University of Technology, Berlin, Germany
“Photonic Localization Techniques” is about die level analysis techniques based on electroluminescence effects of functional anomalies in the DUT. Photon Emission, the most important functional analysis technique in micro- and nanoelectronics to localize active device performance and anomalies, is presented in theory and application. Starting with - The fundamental physics behind the phenomena to understand the functional origin of the light emission in the device, and a - Classification of the effects in various device operation modes, over - Specialities for application through chip backside, to - Dynamic application in Time Resolved Emission (TRE) or PICA techniques, all the important issues will be covered. An outlook of the challenges and opportunities with future technologies will be given with respect to optical resolution, spectral and low voltage issues.
References to complementary techniques like laser stimulation techniques and thermographic techniques will be given.
Beam-Based Defect Localization Techniques
E. I. Cole Jr., Sandia National laboratories, Albuquerque, NM
This workshop reviews conventional and new SEM techniques for IC analysis and new SOM analysis methods. All of these techniques can be performed on a standard SEM or SOM (using the proper laser wavelengths). The use of advanced electron beam test systems will also be discussed. The goal is to provide beneficial information to both novice and experienced failure analysts. Topics are: 1) Standard techniques: secondary electron imaging for surface topology, voltage contrast, capacitive coupling voltage contrast, backscattered electron imaging, and electron beam induced current imaging; 2) Specialized SEM techniques: novel voltage contrast applications, resistive contrast imaging, and charge-induced voltage alteration (both high and low energy versions); and 3) SOM techniques: light-induced voltage alteration, thermally-induced voltage alteration/OBIRCH, Seebeck Effect imaging, soft defect localization, and LADA.
*NEW FOR 2006* Fundamentals of Laser Based FA Techniques
R. A. Falk, Quantum Focus Instruments, Tukwila, WA
Why does shining a laser on an IC locate a short? How can the source of an excess time delay in a digital circuit be determined? There has been an explosive expansion of laser based FA techniques in the last decade, each with their own catchy acronym, e.g. LADA, RDL, OBIRCH, and TIVA. Surprisingly, the underlying physics of these four examples is all the same. This tutorial will explore the fundamental interaction of laser beams with semiconductors and then expand these fundamentals into practical examples. The goal is to demystify laser based FA techniques, to supply the attendee with a basis for interpreting test results and to motivate development of new test approaches to fit the specific failure under investigation.
Focused Ion Beam — A Sample Preparation Tool
K. Hooghan, Hooghan Consultancy and Services, Murphy, TX
In the past decade and a half, Focused Ion Beam systems (FIB) have revolutionized sample preparation in the Microelectronics characterization and failure analysis domain. With submicron accuracy and stress free sections in hard to reach areas, FIB systems have become an indispensable tool in this regard. This tutorial will focus on sample preparation for Scanning and Transmission electron microscopy (SEM/TEM), used for Microelectronics characterization and failure analysis. Different strategies to prepare TEM samples using various Lift out techniques will be discussed, giving the user a broad perspective to make a choice on which tools are available, and make an educated choice in that regard. Materials covered will include Silicon based IC's as well as exotic (InP, GaAs etc.) materials.
Focused Ion Beam – A Design Repair / Fault Isolation Tool
S. Herschbein1, C. Richardson2, C. Rue3, (1)IBM Systems & Technology, Hopewell Junction, NY, (2)Abound Solar, Fort Collins, CO, (3)FEI Company, Hillsboro, OR
Focused Ion Beam (FIB) tools have become a ubiquitous and indispensable part of modern semiconductor Failure Analysis (FA) laboratories. The FIB is the tool of choice for a wide range of FA activities, including fault isolation, circuit edit and design debug, logical-to-physical verification, and stress-free cross sectioning. As such, they can be invaluable in reducing yield learning cycles and speeding product time-to-market. This tutorial provides an overview of some of the most common ‘electrically oriented' applications, with emphasis on the following:
a) General sample preparation, charge control and repackaging considerations.
b) FIB probe pads and in-situ probing for SRAM cell and circuit characterization.
c) Passive Voltage Contrast (PVC) and other fault isolation techniques.
d) Circuit edit and design/layout verification basics - copper and aluminum interconnects, front and backside access, navigation and end-pointing, standard bulk CMOS vs. SOI device construction.
e) The dual beam FIB advantage.
f) Migration of laboratory electrical FIB techniques into the wafer FAB line.
Cost of FA and Debug
S. P. Maher, Oklahoma Christian University, Oklahoma City, OK
Cost of Debug and Failure Analysis (FA) for integrated circuits continues to be an increasing challenge for lab managers and senior technologists, especially for highly integrated devices on leading edge state-of-the-art process technologies. The establishment, operation, and management of a Debug and/or FA Lab require proper perspectives and approaches to maximize the positive impact and cost-effectiveness of the Lab to the product life cycle of the business organization. A holistic approach to the true costs of debug and FA, the various aspects of debug FA Lab operations and business management requirements will be presented.
Failure Analysis Lab Management Overview
R. Ross, Independent, VT
Failure Analysis of electronic components is a highly technical activity, requiring highly skilled personnel, increasingly complex and costly equipment, and the development of increasingly sophisticated techniques and methods to discern the location, nature, and root cause of defects. The establishment and operation of a Failure Analysis laboratory needs to be managed with an eye toward cost-effectiveness and customer satisfaction, while meeting the challenges of a rapidly changing technology environment. At the same time, the career growth needs of the individual analysts, staffing of new personnel, and the development (and cost) of tools/techniques must be addressed. The purpose of this tutorial is to stimulate the attendees to consider the various aspects of Failure Analysis laboratory operations and their respective business management requirements.
*NEW FOR 2006* Lead Free Challenges
V. S. Vasudevan, Intel Corporation, Hillsboro, OR
Government regulations ( EU, China, Japan) necessitated the implementation of Lead Free (LF or Pb free) technology for the second level interconnect. The industry is successfully ramping the LF products across multiple market segments. Critical LF challenges include LF materials and surface finish selection, LF assembly process optimization, mechanical margin reduction; marginality associated material process interaction and reliability margin reduction due to extrinsic factors such as micro voids. This course will cover LF material selection, process window selection, LF surface finish compatibility, backward compatibility and reliability test methods. The course will focus on correlation of material properties and micro structure features to solder joint reliability. The mechanical performance of LF solder joints will be correlated to material stiffness and will be compared with compliant Sn/Pb solder. The differences in the transient bend and dynamic performance of LF solder compared to Sn/Pb solder will be discussed from the fundamental material properties. The effect of material properties on solder joint integrity and reliability will be reviewed. Key reliability challenges such as mechanical margin and solder fatigue performance assessment will be reviewed. The course will also cover various LF failure mechanisms and failure analysis techniques. The impact of PCB related defects such as pad crater and micro voids on LF reliability will be reviewed with examples.
Materials Characterization for Failure Analysis
L. Wagner, Texas Instruments, Dallas, TX
Chemical analysis can play a key role in the understanding the root cause of electronic device failures. The identification of the chemical makeup of particles and contaminants plays a vital role in understanding the sources of these contaminants. This session will provide a basic understanding of the physical principles and examples of applications of the analysis techniques most commonly used in the failure analysis of electronic devices.
The most commonly used technique is Energy Dispersive Analysis which had many advantages for failure analysis. Other techniques such as Auger and X-ray Photoelectron Spectroscopy provide better surface analysis. SIMS is commonly used to provide better sensitivity while techniques like Raman and FTIR provide better identification of organic materials. Other complimentary techniques will also be discussed.
*NEW FOR 2006* Towards Rapid, Low-cost DNA Arrays
S. Zhou, Worcester Polytechnic Institute, Worcester, MA
Handheld molecular diagnostics will become the dominant diagnostic tool for all of medicine once rapid and less expensive detection methods are developed. However, the existing arrays are passive: the motion of DNA in the sample is only governed by diffusion, which make the DNA transport slow and limits the hybridization rate. Electrokinetics is a widely investigated solution to this problem: electrical fields are applied in microarrays, which can induce particles and fluid motion. In addition, traditional molecular diagnostic detection has relied on fluorescent or radioactive labels, and signal transduction is performed with equipment that greatly increases size and cost of the whole system. Electronic detection is expected to involve less complicated and smaller instrumentation while detection limits are maintained. This tutorial will review current efforts developed in the field toward the goal and present new progress performed at Microfluidics and Biosensors Laboratory, Worcester Polytechnic Institute.
Introduction to Microelectromechanical Systems (MEMS) Materials and Fabrication Processes
J. A. Walraven, Sandia National Labs, Albuquerque, NM
Many materials and fabrication processes are used to manufacture microelectromechanical systems (MEMS). Some MEMS fabrication processes such as the MUMPS (Multi-User MEMS Process) and SUMMiT (Sandia's Ultra-planar Multi-Level MEMS Technology) are fabricated using polysilicon, whereas the Digital Micromirror Device (DMD) used in Texas Instruments' DLP is fabricated using thin film aluminum over integrated circuitry. Although many MEMS components are fabricated using these materials, many other materials systems are entering the market or are in development for specific applications. Materials such as polymers, diamond or diamond-like carbon, and silicon carbide are just a few materials being used to develop MEMS technology. This presentation will introduce various MEMS materials systems, MEMS fabrication processes, and a brief discussion regarding the benefits and challenges of each materials system.
Optoelectronic Methodologies for Characterization of MEMS and Electronic Packaging
C. Furlong, Worcester Polytechnic Institute, WPI, Worcester, MA
In this tutorial, optoelectronic techniques for the noninvasive, quantitative, and full-field of view measurement of shape and changes in states of deformation of MEMS and electronic packages are presented. Shape and changes in states of deformation are directly related to the functionality, performance, and integrity of components of interest. With optoelectronic techniques it is possible to characterize, with nanometer measuring accuracy, MEMS and electronic packages subjected to actual operating and loading conditions. Topics covered include, but are not limited to, laser and white light interferometry, Moire, digital holography, holographic microscopy, and confocal microscopy techniques.
Optical and Infrared FA Microscopy
J. J. McDonald, Quantum Focus Instruments Corporation, Vista, CA
An instrument designer discusses the design, use, and limitations for optics based failure analysis tools for circuits. We will discuss conventional microscopes in the FA lab as well as emission microscopes, laser-based microscopes (e.g: OBIRCH, XIVA), and infrared microscopes. We will also cover the “pain and gain” of employing HgCdTe and InGaAs detectors for emission microscopes. Infrared techniques for locating shorts from the back side including OBIC, OBIRCH, LIVA, TIVA, and XIVA laser techniques and locating faults with thermal infrared techniques will be described.
Scanning Electron Microscopy
W. E. Vanderlinde, Laboratory for Physical Sciences, College Park, MD
Learn the underlying theory behind SEM imaging and analysis. Practical tips and tricks will assist in using your SEM effectively. Although the primary focus will be on the theory, operation and value of the SEM, there will also be discussion of recent developments in high resolution electron microscopy to cope with the ever-shrinking dimensions encountered with semiconductor analysis.
Transmission Electron Microscopy for Failure Analysis
S. Subramanian, Freescale Semiconductor, Inc., Austin, TX
A review of transmission electron microscopy (TEM) for failure analysis of microelectronics will be presented. Discussion will include basics of TEM imaging techniques, origin of different image contrast mechanisms and image interpretation procedures for failure analysis of integrated circuits. A brief description of energy dispersive spectrometry (EDS), electron energy loss spectrometry (EELS), energy filtered imaging and scanning transmission electron microscopy (STEM), and their applications in failure analysis will be presented. Several case studies of TEM applications in failure analysis including silicon defects, gate oxide breakdown, electrically resistive interfaces, foreign particles and stringers will be discussed.
Advanced Techniques in Sample Preparation and TEM Analysis of Microelectronic Materials
R. R. Cerchiara1, P. E. Fischione2, J. J. Gronsky2, A. C. Robins2, K. L. Tichenor2, (1)E.A. Fischione Instruments, Inc., Export, PA, (2)E. A. Fischione Instruments, Inc., Export, PA
High resolution STEM of microelectronic and related materials requires samples that are free of artifacts on both the nano and atomic scales. Traditional preparation methods are supplemented by cryogenic ion milling and argon-oxygen plasma cleaning. A variety of side-entry sample holders are available to support subsequent imaging and analysis. These holders include those designed for 3D tomography, holography, electrical biasing of n-p junctions, nanopositioning of probes with respect to the sample surface, and induction of magnetic fields in the plane of the specimen. Imaging in dark field using a high angle, annular detector can support an analysis specific to a particular column of atoms within an engineered material.
Ultra-High Resolution Scanning Electron Microscopy
W. E. Vanderlinde, Laboratory for Physical Sciences, College Park, MD
Rapidly decreasing feature sizes in micro- and nano-electronic devices demand ever higher resolution microscopy tools. The scanning electron microscope (SEM) remains one of the most flexible tools for high resolution imaging. Modern field emission scanning electron microscopes have a nominal spot size as small as 1 nm, but 1 nm resolution is seldom achieved on ordinary samples due to limitations with beam-sample interactions. The limitations on resolution in the SEM will be discussed, and two methods will be presented which overcome these limitations and enable ultra-high resolution: STEM-in-SEM and low-loss imaging.
Enhanced De-Packaging and Chip Access FA Techniques
O. Diaz de Leon, Texas Instruments, Stafford, TX
Enhanced De-Packaging and Chip Access FA Techniques start from the basics of package Failure Analysis applicable to the novice Analyst. These basic techniques include, Manual Decapsulation, Jet Etching, Mechanical de-lidding, and Lapping Techniques. From the basics, newly developed package analysis techniques will be discussed that are important to the experienced Analyst. The enhanced techniques: Top down Chip Access/Tape Pull, Silicon edge lap barrier, Dye'n Pry/Tape Pull combination, Cold Acid Bath for Underfill removal and QFP Backside Cavity Milling; along with the use of optical microscopy and SEM inspection, are critical to the fail mechanism identification of high pin count packages. BGA packages are targeted here as one of the package types that benefit substantially from the development of these new techniques. Detailed procedures of all techniques will be presented.
Chip Scale Package and Its Failure Analysis Challenges
S. Li, Spansion Inc, Sunnyvale, CA
The Chip Scale Package (CSP) is ideal for applications like Cellular and Portable devices, and is widely used for memory device packaging. It has advantages of low package profile, easy routing and superior reliability. However, it also creates more challenges relative to failure analysis and device debugging. This tutorial will describe the unique failure analysis techniques used for these special types of packages. It covers both mechanical and chemical ways to successfully decapsulate the CSP including Multi-Chip Package (MCP), a more advanced CSP used for their reliability advantages in special package structures. You will gain and understanding of the challenges that CSPs create for device handling during failure analysis and device debugging, and learn special decapsulation techniques that are required for this special type of packaging (especially for MCP packages with stacking dices).
Repackaging Complex Devices for Failure Analysis
D. Maxwell, R. D. Harrison, Texas Instruments, Dallas, TX
Packaging is frequently misunderstood and more often underestimated in its effect on product reliability. This presentation will briefly show some of the newest technologies and their advantages and/or disadvantages. The respective characteristics of the newest technologies - advanced packaging and stacked die - that prevent customer PFA and EFA will be presented. Techniques that can be employed to mitigate problems such as power-up isolation and partial EFA will be described. When these methodologies fail to give the required defect isolation with full electrical characterization, repackaging becomes a viable option. With a solid prelude, a detailed answer to “What is repackaging?” will be given. The benefits of repackaging will be provided in the form of case histories, ranging from testing using basic photon emission microscopy to complex debug applications. Concluding remarks will lead the audience into the advantages and disadvantages of new developments in packaging and repackaging of the new technologies.
X-Ray & SAM Challenges for IC Package Inspection
T. Moore, Omniprobe, Inc., Dallas, TX
New challenges are increasing the pressure on packaging and assembly analytical resources. These new pressures impact both fault isolation/failure analysis efforts, as well as package development. Real-time X-ray radiography and Scanning Acoustic Microscopy are the primary tools for nondestructive physical failure analysis of packaged ICs. Today's failure analyst requires rapid inspection of packaged devices with finer geometries, stacked dies and thermal solutions, and often at the board level. The capabilities of these techniques will be compared, and technology improvements required to meet these challenges will be discussed.
Time Domain Reflectometry
D. Smolyansky, Tektronix, Inc., Beaverton, OR
Time Domain Reflectometry (TDR) measurement methodology is increasing in importance as a non-destructive method for fault location in electronic packages. The visual nature of TDR makes it a very natural technology that can assist with fault location in BGA packages, which typically have complex interweaving layouts that make standard failure analysis techniques, such as acoustic imaging and X-ray, less effective and more difficult to utilize. This tutorial will focus on the use of TDR for package failure analysis work. We will analyze in detail the TDR impedance deconvolution algorithm as applicable to electronic packaging fault location work, focusing on the opportunities that impedance deconvolution and the resulting true impedance profile opens up for such work. We will present different techniques for package failure analysis based on the true impedance profile. We will attempt to focus on specific examples and ensure that the attendees will leave with improved understanding of the use of TDR for package failure analysis.
Magnetic Based Current Imaging for Fault Isolation in Die and Packages
L. A. Knauss, Booz Allen Hamilton, Annapolis Junction, MD
Magnetic based current imaging has become a mainstream tool for package level fault isolation of shorts and high resistance defects (resistive opens). This technology is rapidly gaining acceptance for die level fault isolation as well due to recent improvements in resolution. Participants will be introduced to the basics of magnetic current imaging including the two sensors used today, SQUIDs (superconducting quantum interference devices) and magnetoresistive sensors. Applications, using both of these sensors, will be shown at both die and package levels.
From Scan Testing to Embedded Testing
M. Keim, Mentor Graphics, Wilsonville, OR
This tutorial gives an overview of commonly used DFT-kind modifications of logic designs. After a short introduction of the underlying ideas of logic testing, it continues with scan testing and other basic methods. In currently used technologies of 90nm and below, these well-known basic test methods come to their limits: Many different fault modes and increasing quality requirements have caused test pattern sets to become unmanageably large. Throughout industry, embedded test methods are widely accepted solutions of this problem. The tutorial discusses the principle underlying techniques and describes and compares the latest available methods in large detail.
Defect-Oriented Testing
R. Aitken1, A. Gattiker2, (1)ARM, Sunnyvale, CA, (2)IBM Corporation, Austin, TX
This tutorial presents an overview of defect based testing. Electrical behavior and circuit effects of CMOS IC defects and failure mechanisms are described, and test methods that can be effective in detecting them are overviewed. Basic fault models that represent those defects are discussed, along with how they can be used in test generation, test evaluation and defect localization. We also address how to apply defect based testing in production, including the use of design-for-test (DFT) features such as serial-scan and BIST.
Logic Diagnostics: Techniques, Applications and Challenges
S. Venkataraman, Intel Corporation, Hillsboro, OR
Covers the state of the art and the full spectrum of topics in defect diagnosis ranging from the basic concepts, real world application to future challenges. After a brief review of the basic concepts and applications of diagnostics over the life-cycle of a product, the established diagnosis procedures will be discussed, including fault dictionaries, post-test fault simulation, and hardware-based backtracking. Next, recent enhancements and advanced diagnosis topics will be covered, including methods for locating defects such as opens, shorts, and leakage in transistor-level circuits, approximation techniques for identifying unmodeled faults, deductive analysis, Iddq-based diagnosis, diagnosis for delay-faults, Scan-chain diagnosis, BIST-based diagnosis, and design-for-diagnosability techniques. A focus on Silicon debug techniques, design-for-debug techniques, and applications to yield improvement will follow. Successful diagnosis methods used in real industrial products, industrial experiences and case studies will be described, as well as future challenges.
FA Case Histories using ATPG and SCAN Diagnostics
K. S. Wills, Independent Consultant, Sugar Land, TX
SCAN is a technique to locate a failure to a specific set of logical nets. Often the result is a set of nets that is too large in number to be helpful or the resultant net is too long to be useful. Even when the net is of reasonable size more information about the defect is important to further isolate the defect. Non-destructive techniques well known in the semiconductor industry can be used to compliment the SCAN results. Techniques such as Thermally Induced Voltage Alteration (TIVA) or Photon Emission (PE) can correlate an area of the die to the failing mode. Oddly enough there have been instances where C Mode Scanning Acoustic Microscopy (C-SAM) have helped compliment the SCAN data even though the technique does not measure the electrical properties of the device under test. Case studies will be presented showing how these techniques compliment SCAN. The Physical Failure Analysis results will be given for the case studies discussed.
Yield Basics for Failure Analysis
T. Myers, J. Hanson, ON Semiconductor, Gresham, OR
Wafer fab yield is a driving force for many FA activities and can originate from fab process interactions, fab defects, design issues, reliability fails and customer returns. This presentation will provide an overview of various types of yield issues and sources of yield loss. The difference between systematic and random yield loss mechanisms will be described. Common terminology and general approaches to yield analysis and yield improvement will be discussed. Several case studies that involved failure analyis to help resolve yield issues will be given.