Investigations on the Influence of Focused Electron Beam on Electrical Characteristics of Integrated Devices
S. Doering, R. Harzer, W. Werner, Qimonda Dresden GmbH & Co. OHG, Dresden, Germany
Our data confirms the effect of electron beam induced alteration of integrated devices. It could be shown that several parameters influence the investigated device like beam acceleration voltage and dose used for radiation. It is also shown that several device parameters are affected. Differences to the unexposed transistor are visible for IOFF, IL and ION as well as for the VTH. Whereas the device leakage currents increase with higher exposure, the ION values decrease. The VTH values shift to higher values. From our point of view the increase of the IL can be explained with trapped electrons at the interface between gate oxide and active area. Since charge carriers are available at the transistor channel the conductivity between the source drain regions is increased leading to a raised leakage current. The decreasing of ION currents might be explained by an increase of the resistance of the source drain regions whether to the underlying nwell or to the connecting source-drain contact. Diode characteristics of the source drain contacts to the nwell support this hypothesis. It is also shown that the electron beam irradiation leads to gate oxide degradation. In conclusion and as an answer to our initial questions it is possible to state that measurements with our available SEM based prober are possible, but under certain SEM parameters as low VACC and low doses. Only at those SEM parameters the electron beam influence on electrical device parameters is negligible. Our studies also show that it is from major importance to know the sample history before electrical device characterizations are carried out. This is due to the electron beam induced device parameter changes are nearly unaltered over a long period of time after the beam exposure.
Combine Nano-Probing Technique with Mathematics to Model and Identify Invisible Failure
C. M. Shen1, T. C. Chuang2, S. C. Lin2, C. M. Huang2, L. F. Wen2, (1)Taiwan Semiconductor Manufacture Company, Ltd., Taiwan, Hsin-Chu, Taiwan, (2)Taiwan Semiconductor Manufacture Company, Ltd., Tainan, Taiwan
The utilization of Nano-probing could acquire detailed electrical data, and the reasoned simulation by various mathematic models would imitate all the significant failure characteristics. So the defect mode could be identified out even when the general PFA could not be implemented for several non-visual defect modes.
Failure Analysis of DC Failure in Advanced Memory Devices using Nanoprobing and Scanning Capacitance Microscope
J. L. Lue1, C. S. Lin2, A. Chiou3, H. Liu1, B. Pai1, S. Fan1, T. Wang1, (1)ProMOS Technologies Inc., Hsinchu, Taiwan, (2)ProMOS Technologies Inc., Tajchung County, Taiwan, (3)ProMOS Technologies Inc., Taichung County, Taiwan
Discuss the failure analysis process of a DC failure using an in-FIB (Focused Ion Beam) nanoprobing technique with four probes and a scanning capacitance microscope (SCM) in advanced DRAM devices. The I-V curve shows a high leakage current at a lower threshold voltage in the failed P-MOSFET device. The cross-sectional 2-D doping profile of SCM indicates the region of P-Well bridges the drain region of the failed device that might cause the DC failure in the electrical test.
Measuring Static Noise Margin of 65nm node SRAMs using a 7-point SEM Nanoprobing Technique
R. E. Stallcup1, Z. Cross1, W. James2, P. Ngo2, (1)Zyvex Corporation, Richardson, TX, (2)Microtech Analytical Labs LP, Plano, TX
In this paper we report, for the first time, a technique for measuring the static noise margin (SNM) of in die 6T SRAM bit cells using an SEM based nanoprobing system. The SNM of a bit cell quantifies the amount of electrical noise that is required, at the cell’s internal nodes, to flip the cell’s contents. [1,2] This information is vital to the engineering cycle to produce faster and more efficient SRAM designs. With the aid of SEM based nanoprobing systems that are equipped with 8 or more probes, measurements such as SNM and bit cell stability are now possible on in-die SRAM transistors.
Localized Die Metallization Damage Induced during Laser-marking of a Semiconductor Package
P. E. B. Paranal, Intel Technology Philippines, Inc., Gen. Trias, Cavite, Philippines
This paper presents a new fail mechanism for laser-marking induced die damage. Discovered during package qualification, silica spheres – commonly used as fillers in the molding material, was shown to act as a propagation medium that promote the direct interaction of the scribing laser beam and the die surface.
A Novel Technique for Determining the Location of a Hermetic Leak in a ‘Metal Can' (TO-x) Package
C. M. Nail, Independent, San Jose, CA
Pressurized dye penetrant by itself does not always successfully locate leaks. Metallographic preparation of the failed seals, combined with vacuum storage, more effectively decorates the defect at the surface of the prepared seal at the leak location.
BGA Package Level Failures Due to Contamination
J. A. Roepsch, Raytheon, McKinney, TX
Two case studies will be discussed in which root failure cause was related to process issues at the supplier. Contamination on raw PWBs resulted in poor solderability at the package level. In the first case study, a photoresist material used to protect the solder on one side of the board as the other side was being etched was not completely being removed. A plasma clean was sufficient in cleaning the photoresist from the solder allowing boards in stock to be used. The board supplier changed processes on future builds by etching both sides of the board simultaneously eliminating the need for the photoresist. No future failures were identified after this process change. The second case study also was a failure initiating at the supplier. Material was trapped in vias due to their small feature size, later leaching out onto the board surface. The source of the carbonate material was never fully understood but could be isolated to the supplier. Once the vias were filled by the supplier, future failures were no longer identified. A rework process involving 10% HCl was carried out on failed CCAs improving the solderability with replacement BGAs.
Failure Analysis Methodology of Li-Ion Incidents
J. D. Loud1, X. Hu2, (1)Exponent Failure Analysis Associates, Menlo Park, CA, (2)Exponent Failure Analysis Associates, Natick, MA
The consumer product industry continues to show more and more demand for portable electronic devices that require stored electrical energy. Li-Ion battery technology has become the most popular choice because of its high energy density, high cell voltage, low self-discharge rate and no “memory effect” on its capacity. However, it is the high energy density inherent in Li-Ion batteries that can result in unsafe failures. Failure can occur due to problems within a cell, or because of external factors that impact a cell. Undesired failures range from inconvenient overheating of the cell that causes minor damage to surrounding materials, to energetic venting with flames. While these potential failures have been known and explored for many years, it is only with the proliferation of these devices in society that these undesirable, low probability events are gradually becoming known. Extensive efforts have been devoted to reducing the probability that such events will occur, including external circuit protection to prevent electrically-induced events, and novel cell designs and manufacturing methods to prevent failures. The need is great, however, to conclusively establish the cause of such undesired events so that steps can be taken to prevent future events and also to determine whether a field population has an unacceptably high risk of failure and should be removed from service. Understanding the failure mechanisms of a lithium ion cell and the root causes of the failure is very important in establishing a complete fault tree. Possible causes for a Li-Ion failure include: 1. An internal cell short circuit (manufacturing-related). Possible causes of an internal short circuit include: a. A burr or other metal processing anomaly that stresses the separator and eventually results in an electrode-to-electrode short circuit. b. Contamination in the jellyroll that eventually penetrates the separator, resulting in an electrode-to-electrode short circuit. c. Contamination in the jellyroll that dissolves, plates out on the separator and dendritically grows through the separator, resulting in an electrode-to-electrode short circuit. d. A lead anomaly that stresses the separator and eventually results in an electrode-to-electrode short circuit. e. Misalignment of the winding such that contact between the electrodes (including active materials) occurs. f. A lead to case or lead to jellyroll short circuit. The routing, length and insulation on the leads that bring the cell power out of the cell is important to prevent short circuits. 2. An internal cell short circuit (externally caused). Possible causes for such an event include: a. External mechanical crush of the cell can. b. A pinpoint dent in the cell can. c. Excessive mechanical impact. 3. An external cell short circuit. The routing and insulation on the external leads is important to prevent external short circuits. 4. Overcharge of the cell. Overcharge of the cell may result in internal heating and precipitate a cell internal short circuit. Such internal short circuit events may be quite energetic since the amount of energy stored at the time of the incident is higher than that of a fully charged cell. 5. Overdischarge of the cell. Overdischarge of the cell will result in dissolution of the copper current collector and subsequent plating of the dissolved copper onto the adjacent separator. Repeated overdischarge will result in dendrite growth of the copper through the separator and eventually an electrode-to-electrode short circuit. 6. Electrode degradation. A local anode-to-cathode imbalance can cause localized degradation (oxidation) of the electrodes. The oxidation process will generate heat as well as gasses that will diffuse to the adjacent electrode and cause additional oxidation. This process may result in cell overheating and venting. 7. External heat. Externally heating a cell will cause it to fail such that it will vent to dissipate its energy in an undesirable manner. There is a wide range of damage that occurs in Li-Ion incidents. The goal in a root cause failure analysis is to identify the surviving characteristics present in the remaining evidence to determine which of the above caused each incident. However, because of the nature of a Li-Ion incident, it usually results in charred or burnt material. There is often only limited surviving evidence for the failure investigator to evaluate. Since 1996, when the authors first became involved in evaluating Li-Ion incidents, they have developed and refined a systematic methodology through numerous Li-Ion incident investigations. This methodology, which is tied to the above fault tree, is described as follows: 1. System level visual inspection looking for evidence of: a. External heating/fire attack, b. Mechanical impact or compression, or c. Liquid intrusion, etc.; 2. System level X-ray inspection of the protection circuitry, looking for evidence of circuit or component failure; 3. Protection circuit/charge circuit functionality testing; 4. Cell level X-ray inspection to characterize the damage pattern of the incident cell and prepare for destructive inspection of cell remains; 5. Cell disassembly and microscopic inspection of cell remains: a. Evaluate overall damage pattern of remaining cell electrodes; b. Microscopic inspection of copper electrode, looking for signs of melted copper; 6. Supplemental analysis may include: a. EDX (Energy-dispersive X-ray spectroscopy), looking for potential contaminants; b. XRD (X-ray diffraction) analysis of remaining active material in evaluating potential overcharge conditions; c. Replication testing; d. Survey of exemplar cells; e. Review of manufacturing operations; f. Statistical analysis of failed units. This paper presents detailed explanations of each step in combination with typical photographs from selected representative incidents. This paper can be used as a guideline for investigators in Li-Ion incident failure analyses.
Case Study and Fault Modelling for Wrong Redundancy Evaluation on DRAM Devices
M. Versen1, D. Diaconescu2, J. Touzel2, (1)University of Applied Sciences Rosenheim, Rosenheim, Germany, (2)Infineon Technologies AG, Munich, Germany
The paper presents a case study of a bitline oriented failure mode connected to a redundancy evaluation in the DRAM periphery. The failure mode analysis and fault modeling focus both on the root-cause and on the test aspects of the problem.
Fault Isolation of Soft P-N Junction Break Down Due to Plasma Charging
D. T. Nguyen, T. Dudar, Texas Intruments, Inc., Dallas, TX
A typical failure of a differential amplifier can be measured by Output Offset (OO) voltage. However, when the offset voltage is well within spec, the failure can be difficult to detect. Moreover, in a case where emitters are connecting in parallel to make up a large BJT for a differential amplifier, a leakage in one of the hundred of parallel emitters would degrade the performance of the whole differential pairs. In one case, single emitter failure caused OO, but in another, the only way to detect the failure was to monitor the final stage of the output. The paper will outline the test techniques to detect the differential OpAmp failure, circuit analysis (design and simulation), fault isolation, and root cause analysis with data from the fabrication to support plasma charging on emitter-base junction. This differential OpAmp is a typical one with feed back loop, current/voltage bias for the differential pairs, and outputs to the second stage, etc. In a case of a large BJT, which was laid out by the used of 240 emitters connecting in parallel. When one of the 240 parallel emitters failed, it degraded the performance of the differential OpAmp.
Tool-Related ESD Surface Damage (ESDFOS) on Wafers in Cu Technology
P. Jacob1, C. Hartfield2, (1)EMPA Swiss Federal Laboratories for Materials Testing and Research, Duebendorf, Switzerland, (2)Omniprobe, Inc., Dallas, TX
ESDFOS (ESD From Outside to the device Surface) has been intensively researched on semiconductor wafers fabricated with aluminum interconnects. ESDFOS is often misdiagnosed and the root cause of the ESDFOS physical signature, damaged passivation, attributed to “mechanical damage”. However, many of the ESDFOS-damaged passivation areas are barely visible, even by SEM, with dimensions on the passivation surface of a few microns. In previous work, a series of artificially induced ESDFOS (using a Wimshurst machine) proved that small area “mechanical impact” damage was in fact caused by electrostatic discharge into the passivation, generating interlevel shorts within the two top metal layers [1, 2]. This enabled identification of process causes of ESDFOS and development of methods to reduce it [3, 4]. ESDFOS signatures on devices with Cu metallization have not been investigated. If the ESDFOS damage signature on devices with Cu interconnect does not match the damage signature from Al interconnect devices, then ESDFOS impacts will likely not be identified. Since manufacturing steps contributing to ESDFOS on Al devices are also common for Cu technology, there was a need to investigate the ESDFOS sensitivity of Cu-technology devices.
Detection and Verification of Silicide Pipe Defects on SOI Technology using Voltage Contrast Inspection
O. D. Patterson1, K. Wu2, H. Kang3, J. Strane1, C. Lavoie1, K. Barth1, X. Ouyang1, (1)IBM Corporation, Hopewell Junction, NY, (2)KLA-Tencor, Hopewell Junction, NY, (3)IBM Systems & Technology, Hopewell Junction, NY
This paper discusses the detection of silicide defects on SOI technology using voltage contrast inspection. The technique offers faster feedback, isolation of the exact defect location, and is useful for partition analysis to track the evolution of these defects. These defects are not visible to other tools and so the technique to accurately FIB mark these defects for planview analysis is highlighted.
Photo Process Margin Leading To IC Failures- A case Study
V. Chowdhury, C. Hsu, A. Yu, Altera Corp., San Jose, CA
Subtle read disturb failures seen on several lots and products had a pattern specific failure. A thorough layout analysis followed by nanoprobing confirmed the failure to be specific to certain transitors with a poor performance. The uniqueness of the layout made the failing rows and columns more vulnerable to this failure. A correlation done with the impact lots confirmed the failures due to a bad tool. The column and row failures were ascribed to blocked NLDD and pocket implant
Failure Analysis of Multi Finger HV Symmetric Device for Charge Pumping Circuit Application
L. F. Wen1, D. J. Wang2, C. H. Chen3, (1)TSMC, Hsin Chu, Taiwan, (2)TSMC, Hsin-Chu, Taiwan, (3)National Taiwan University, Taipei, Taiwan
The purpose of this paper is to present a systematic analysis methodology on new taped out High voltage (HV) product, which is encountered ~0% yield issue. In order to find out the root cause and improve the yield, a series of electrical analysis experiment to reveal the failure phenomenon of charge pumping circuit was applied. Combining the spice simulation data, I-V curve measurement, C-AFM measurement and nano probing, the resistance difference on multi finger symmetric device was revealed. And then deductive method on layout analysis and in-line split experiment were developed to explain the failure phenomenon that multi finger HV symmetric device for charge pumping circuit.
Cu Voiding in 90nm Technology Through Photovoltaic-Driven Electrochemical Dissolution
J. DeLucca, F. A. Baiocchi, J. T. Cargo, LSI Corporation, Allentown, PA
PCB Related Field Failures with ImAg Surface Finishes
A. Kurella, A. Munukutla, J. Lewis, Intel Corporation, Hillsboro, OR
PCB surface finishes like Immersion silver (ImAg) are gaining popularity in Pb-free manufacturing environments following RoHS legislation. With this transition, however the numbers of field failures associated with electrochemical migration, copper sulphide corrosion, via barrel galvanic corrosion are on a steady rise. As computers penetrate into emerging markets with humid and industrialized environments there is a greater concern on the reliability and functionality of these electronic components. The present paper focuses on different modes of failures, root causes and discusses possible solutions to these problems.
Laser Based Failure Isolation Techniques
F. Arnold, Texas Instruments, Dallas, TX
Series Capacitance in High Speed Differential Pairs, a Failure Analysis Case Study
N. Konkol, Intel Corporation, Hillsboro, OR
Series capacitors, under certain conditions, within high speed differential pair signals can have negative effects on mother board functions inside a personal computer (PC). One failure analysis case study found those conditions.
Concepts for In Situ Diagnostics in Analog Microelectronic Circuits
T. Kolasa, A. Mendoza, Freescale Semiconductor, Tempe, AZ
This paper will present ideas for incorporating full coverage in situ diagnostics into analog circuit designs.
Wireless Advanced Failure Analysis Tool
T. F. Chee1, M. Zhang2, (1)Intel Products (M) Sdn Bhd, Kulim, Malaysia, (2)Intel Corporation, Hillsboro, OR
Wireless Advanced Failure Analysis Tool (WAFT) is designed with purpose to provide cost effective FA solution for all kind levels engineers/manufacturing debugs in performing FA on Intel MIMO product.
Low KeV Applications for FIB Circuit Edit
C. Rue, FEI Company, Hillsboro, OR
The effect of ion beam acceleration potential during FIB processing is examined for several gas-assisted processes. A discussion of the hardware challenges associated with low keV operation is also presented.
Quantifying the Benefit of Ion Beam Defocus for Circuit Edit Applications
K. Skinner1, M. DiBattista1, R. Kneedler1, L. Vasilvey1, L. Drybak1, J. Zbranek1, G. Hartigan2, M. Oosting2, (1)FEI Company, Hillsboro, OR, (2)FEI Company, Eindhoven, Netherlands
As FIB based circuit edit technology matures, the demands for faster processing steps increase to meet the high throughput expectations from customers, yet the scaling of semiconductor process technologies require more controlled processes and improved materials property control in order to maintain lab success rate. This paper will demonstrate the process enhancements of ion beam defocusing on the traditional circuit activities of metal and dielectric deposition and Si and SiO2 etching. The gas precursors for this study include tungsten hexacarbonyl [W(CO)6] for metal deposition, tetramethylcyclotetrasiloxane [TMCTS] and oxygen [O2 ] for dielectric deposition, and xenon difluoride [XeF2] for etching. To quantify the analysis, we have employed a statistical based design of experiments (DOE) incorporating a select range of beam parameters including the beam dwell time, pitch, and precursor pressure in combination with the lens two defocus.
Couple Circuit Edit Skill with OBIRCH Technology to Locate Unrecognizable RF and Mixed-mode Failure
C. M. Shen1, T. C. Chuang2, L. F. Wen2, S. C. Lin2, C. M. Huang2, (1)Taiwan Semiconductor Manufacture Company, Ltd., Taiwan, Hsin-Chu, Taiwan, (2)Taiwan Semiconductor Manufacture Company, Ltd., Tainan, Taiwan
This paper is to present a composite methodology to overcome the special failure in RF integrated circuit, which cannot be localized by general failure analysis method or instrumentation directly.
Comparison of Passive and Active Voltage Contrast for Failure Localization
R. Rosenkranz, W. Werner, Qimonda Dresden GmbH & Co. OHG, Dresden, Germany
The Voltage Contrast localization methods became widely accepted in the semiconductor failure analysis community during the last decade and nearly all labs make use of it. Because of the fact, that Passive Voltage Contrast localization has its limits, this method is compared with the Active Voltage Contrast localization method. Advantages and disadvantages of both methods are shown and are illustrated with case studies.
Latch-up Root Cause Analysis for new ASIC Design
W. Danielak1, S. Waldstein1, W. Machado1, A. Jordan1, M. Jaffer1, M. Sachdev2, D. Li2, (1)Tundra Semiconductor Corporation, Ottawa, ON, Canada, (2)University of Waterloo, Waterloo, ON, Canada
Latch-up is defined as creation of an unintentional, low impedance path between power supply and ground in bulk CMOS integrated circuits (ICs). Latch-up in an IC can be destructive if the current is not restricted, hence it should be avoided at all costs. With the new ASIC designs based on the library IP (Intellectual Property) from different vendors, standard IP validation based on the test chip is not sufficient. For the analyzed case of new IC design it is worth to mention that five previous chips had used this library IP without having the latch-up problem. Unique cell combination and device operation at multi-domain power supply voltages can cause the latch-up phenomenon. The analyzed ASIC device is based on 130nm CMOS technology, operates at three power supply levels (1.2V, 1.8V and 3.3V) with two ground domains (Vsscore and VssoIO) and is assembled in 1025 pins FCPBGA (Flip Chip Plastic Ball Grid Array) package. The device failed the latch-up test on two pins (K5, L8). In order to determine the root cause, the Failure Analysis (FA) with use of backside EMMI (Emission Microscopy) was performed. It was found that the root cause of the latch-up is an abutment of two specific cells (cell C and cell D), where the N-well was grounded creating a parasitic NPN transistor sustaining the latch-up. A detail calculation of parasitic resistances from the layout revealed some differences between latching and non-latching pins. The analytical model to explain the latch-up behavior based on parasitic resistances was developed and applied successfully to root cause analysis. In final conclusions, the design recommendations on how to eliminate latch-up triggering and sustaining mechanisms were made, and DRC script was developed to check the abutment of specific cells. The paper is complete and ready for submission. Any details are available on reviewer’s request.
Analysis of Bridge Failure between PPG and LPP in Fin Cell Transistor
J. H. Lee, Hynix semiconductor, Icheon, South Korea
As a promising candidate for DRAM scaling beyond 40nm technology, the fin cell transistor (FCT) utilizing p-type poly silicon gate (PPG) was proposed. However FCT makes a lot of bridge failure between word-line and landing-plug poly (LPP) connecting source and drain regions in a cell transistor. But this bridge point is so insignificant that the failure was hardly detected by existing read modify write (RMW) pattern. We analyzed this failure with a particular test method. It mostly has been observed to single and odd parity address. We found out that when adjacent gate is active for reading its cell, only the forward bias can run into the LPP with n-type poly-silicon, and low status data would be taken high level turn unlike recess cell array transistor utilizing n-type poly silicon gate (RCAT-NPG) which both high and low status would be reversed.
Silicon Dislocation Enhanced by Dynamic Voltage Stress
Y. C. Lin1, M. Li1, R. Chen1, S. Liang2, S. Liao1, C. Niou2, W. T. K. Chien1, (1)Semicoductor Manufacturing International Co., Shanghai, China, (2)Semiconductor Manufacturing International (Beijing) Corp, Beijing, China
In reliability test some chips suffered functional failure. Through a series of failure analysis, the root cause of such failure is considered to be silicon dislocation across LDD area causing p-n junction leakage. However, those failed samples all passed both CP (Chip Probe) and FT (Final Test) monitor. Therefore, it is reasonable to suspect that DVS (dynamic voltage stress) may enhance minor dislocation already existed before CP and FT. To approve hypothesis mentioned before, a series experiment was designed to find the relationship between DVS and the depth of dislocation in silicon substrate. In conclusion, DVS could enhance dislocation across LDD (Lightly Doped Drain) area, which may induce reliability failure. Moreover, this finding on reliability concern will be discussed in this paper.
Effects of Backside Circuit Edit on Transistor Characteristics
R. K. Jain1, T. Malik2, T. R. Lundquist1, Q. S. Wong1, (1)Credence Systems Corp., Sunnyvale, CA, (2)DCG Systems Inc., Fremont, CA
The IC community has often wondered about the effects of a backside circuit edit using a FIB on IC behavior. Reliability of silicon device structures, transistors and diodes, are investigated by monitoring intrinsic parameters before and after and though each step of the circuit modification.
FIB Backside Circuit Modification on Device Level Allowing to Access Every Circuit Node with Minimum Impact on Device Performance by use of Atomic Force Probing
R. Schlangen1, U. Kerst2, C. Boit2, S. Schomann3, B. Krueger3, R. K. Jain4, T. Malik4, T. Lundquist4, (1)TUB Berlin Institute of Technology, Berlin, Germany, (2)TUB Berlin University of Technology, Berlin, Germany, (3)Infineon Technologies, Munich, Germany, (4)Credence Systems Corporation, Sunnyvale, CA
Direct measurements, connecting to central circuit nodes without changing the performance of the circuitry are critical in modern FA but often impossible for recent IC technologies. This paper shows new methods based on FIB backside circuit edit, allowing to reach every circuit node existing on device level and discusses the offered options for probing and discrete characterization.
Deposition of Narrow, High Quality, Closely Spaced, but Isolated Conductors
V. V. Makarov1, R. K. Jain2, (1)Tiza Lab, LLC, Milpitas, CA, (2)Credence Systems Corp., Sunnyvale, CA
We developed procedures to deposit narrow, low resistance Molybdenum conductors including electrical isolation when closely spaced. To isolate adjacent conductors, a procedure is applied enabling efficient removal of the over-spray and protecting dielectric between conductors in contrast to highly used XeF2
Challenges of Atomic Force Probe Characterization of Logic Based Embedded DRAM for On-Processor Applications
T. Kane1, M. P. Tenney1, A. N. Erickson2, S. Phan2, (1)IBM, Hopewell Junction, NY, (2)Multiprobe, Inc, Santa Barbara, CA
The emergence of multiple core, high speed microprocessors in 90nm node technologies has been dominated by SRAM on-processor cache. However, by employing Logic based on-processor embedded DRAM cache in 65nm SOI applications, limitations in SRAM cache involving standby current, requirements for error correction circuity to address soft error rate (SER), and Vmin cell stability can be overcome.1-14 Reported high performance embedded DRAM 65nm SOI designs with ~ 1.5ns latency and < 2ns random cycle characteristics are enabled by strain engineered pass transistor with optimized source/drain junctions for sub-pA off currents.1-12 Implementing a deep trench capacitor design versus a plate type design for embedded DRAM cache in these SOI designs means less mask steps (with lower cost) accompanied by a significantly smaller DRAM cell size.1-2 The embedded DRAM cell size for 65nm SOI cache designs measures 0.127 ƒÝm2 and for 45nm SOI cache measures 0.067 ƒÝm2 . These embedded DRAM cell sizes dramatically increase cache capacity (2Mb and 4Mb cache reported) while simultaneously reducing cost, power consumption, soft error sensitivity while fitting in a smaller size footprint.1-2 The challenges to electrically characterize discrete DRAM cells as small as 0.067 ƒÝm2 in these embedded 2Mb caches requiring femto amp current sensitivities are not trivial.ƒ¡ƒ&brkbar;ƒzƒ¡ƒ§ Six probers are required to contact all nodes and four AFP probers placed within a 0.067 ƒÝm2 cell area with femto amp current sensitivity. DRAM cell retention time tests lasting up to ten minutes for femto-amp current sensitivities pose challenges for AFP contact measurements.
Alternating Plane-View and Cross-Section Scanning Capacitance Microscope Technique to Reveal Various Implant Issue
T. C. Chuang1, C. M. Shen2, (1)Taiwan Semiconductor Manufacture Company, Ltd., Tainan, Taiwan, (2)Taiwan Semiconductor Manufacture Company, Ltd., Taiwan, Hsin-Chu, Taiwan
This paper illustrates that correct selection from either plane-view or cross-sectional SCM analysis according to the surrounding of defect could help to exactly and rapidly diagnosis the failure mechanism. X-SCM could make vertical profile analysis but it need precise defect position just like clockwork. PV-SCM could navigate at suspected roomy space and efficiently reveal defect to reduce FA cycle time. But it could not provide deeper implant information due to the “plane” by birth. Altering and optimizing PV-SCM and X-SCM techniques to navigate various implant issue could provide correctly actions that suit local circumstance of defects and ratiocinate failure mechanism to a nicety.
Sub-Zeptofarad Sensitivity Scanning Capacitance Microscopy Sensor
H. Dongmo, P. Hammond, J. Weaver, University of Glasgow, Glasgow, United Kingdom
We describe A 3 GHz sensor for SCM with sub-zeptofarad sensitivity. The sensor is based on the designs of Tran et al. PCB Prototype is being used as a test bed and the first step towards a single-chip SiGe BiCMOS SCM presently being developed at the James Watt Nanofabrication Centre (JWNC) of the University of Glasgow.
Backside 3D Analysis of Power Device Using an ITO Electrode
Y. Goto, Toyota Motor Corporation, Aichi, Japan
The power device has a vertical structure and analysis of defective products generally occurs from the backside because the surface is covered in an aluminum electrode and the backside in a metallic electrode. We will discuss the development of backside 3D analysis technique using defective products that emerged due to the marginal valuation of the power device development. First, it was verified that applying a DC voltage uniformly to the entire backside would be effective in placing a glass with an ITO transparent electrode in contact with the backside; therefore it was able to specify a failure point using the IR-OBIRCH method. Then, a micro-sample was extracted without missing the failure point and observed the 3D perspective method; thus it was clear that existence of crystal lattice defects were thought about as the cause of failure.
Re-Thin a TEM Lamella by Using a Novel TEM Sample Preparation
C. R. Chen, Material Science Service Corp., Hsin-chu, Taiwan
This is a solution to reprocess TEM lamella if specimen is too thick to observe the nano-structure and too much ion damage results in the amorphous sidewall effect. In addition, it can eliminate the carbon signal comes from the carbonfilm supported grid for EDS analysis.
Applications for Parallel Grinding as an Alternative to Chemical Decapsulation in Preparing Packaged Samples for Failure Analysis
C. M. Nail, Independent, San Jose, CA
Chemical decapsulation can introduce undesirable artifacts. Mechanical grinding can reliably remove package material to a given depth without these artifacts, permitting later preparation and analysis with undamaged and uncontaminated samples.
Three-Dimensional Nanometric Sub-Surface Imaging of a Silicon Flip-Chip using the Two-Photon Optical Beam Induced Current Method
E. Ramsay, K. A. Serrels, M. J. Thomson, A. J. Waddie, R. J. Warburton, M. R. Taghizadeh, D. T. Reid, Heriot-Watt University, Edinburgh, United Kingdom
We have achieved three-dimensional imaging inside a silicon flip chip by implementing two-photon optical-beam-induced-current microscopy using a solid-immersion lens at a wavelength of 1530nm. This technique allows diffraction-limited lateral resolution of 166nm and an axial resolution capable of resolving features only 100nm in height.
Near-IR Photon Emission Spectroscopy of Strained and Unstrained 60 nm Silicon nMOSFETs
S. L. Tan1, K. W. Ang1, K. H. Toh1, D. Isakov1, L. S. Koh2, C. M. Chua2, Y. C. Yeo1, D. S. H. Chan1, J. C. H. Phang1, (1)National University of Singapore, Singapore, Singapore, (2)SEMICAPS PTE LTD, Singapore, Singapore, Singapore
Near IR Photon Emission Spectroscopy were performed on 60 nm strained and unstrained nMOSFETs. There are significant differences between the spectra of the strained and unstrained nMOSFETs. These differnces could be due to the strain in the channel of the strained nMOSFETs
Failure Localization and Design Debug on Mixed-Mode ICs by using the Dynamic Laser Stimulation Techniques
M. A. Sienkiewicz1, K. Sanchez2, A. Firiti3, O. Crepel4, P. Perdu2, (1)CNES (French Space Agency) (& Freescale Semiconductor), Toulouse, France, (2)CNES - French Space Agency, Toulouse, France, (3)Freescale Semiconductor, Toulouse, France, (4)Freescale Semiconductor SAS, Toulouse, France
Nowadays, the laser stimulation techniques have a wide field of application for failure localization and design debug. The static techniques such as TLS (Thermal Laser Stimulation) and PLS (Photoelectric Laser Stimulation) are commonly implemented in the industrial equipment. In the TLS, the device is heated with a 1300nm infrared laser beam to localize the abnormal resistive issues. In the PLS, a 1064nm wavelength laser, scanning the device, contributes to the electron-hole pairs generation in active areas (silicon) and, as consequence, to the additional photocurrent injection [1], [2], [3]. The results of a severe technology progression are: device miniaturization, increasing number of metal layers as well as interconnections and voltage reduction. Moreover, the evolution of mixed-mode ICs shows that the surface area of the digital blocks increases compared to the area of the analog blocks. In addition, a complex interface circuitry is integrated between analog and digital areas. These key points make more complex failure analysis on the mixed-mode devices presenting a functional failure. Static laser stimulation techniques are limited and are not able to localize this type of failure. Consequently, new techniques and tools are required to localize sensitive or failing regions. Recently, new and various dynamic optical techniques based on laser stimulation have been developed and introduced in failure analysis laboratories of semiconductors industry and research, like: SDL [4] (Soft Defect Localization), LADA [5] (Laser Assisted Device Alteration), DVM [6] (Delay Variation Mapping) etc. Which one do we have to choose to make the analysis efficient with the shortest cycle time? The issues described in this paper are based on the work done in collaboration between Freescale Semiconductor and CNES (French Space Agency). Experimental results presented here were obtained on a complex mixed-mode IC from Freescale. These devices, designed in SmartMOS technology, are particularly complex. It is important to underline the singularity and complexity of Freescale device’s because they include on the same chip digital, analog, RF and power electronic applications, plus several interfaces circuitries between them. So we have to take into account all these aspects for electrical diagnostic and failure analysis, which requires a different approach in term of defect localization and design debug in comparison to pure CMOS technology devices. This paper will treat diverse methodology applied on mixed-mode advanced Freescale ICs to localize sensitive areas and to support design solutions in the industrial context of TtM (Time to Market). This abstract presents one case study of a soft defect, successfully resolved with a help of DTLS (Dynamic Thermal Laser Stimulation) [7].
Al Pad Corrosion Mechanism Study when Dicing Saw
S. Duan1, M. Li2, Q. Yu1, J. Su3, S. Lin1, C. Niou3, K. Chien2, (1)Semiconductor Manufacturing International (Shanghai) Corp, Shanghai, China, (2)Semicoductor Manufacturing International Co., Shanghai, China, (3)Semiconductor Manufacturing International (Beijing) Corp, Beijing, China
Bad corrosion was found at the edge area of wafer pad under OM images after dicing saw. Experiment showed that the corrosion was related with the feed speed of dicing saw. From SEM and OM results, there were some abnormal contaminations around the corrosive area. Auger and TEM with EDX system were used to characterize the corrosive region and the related Al pad corrosion mechanism was discussed. In this paper, Cu rich and O rich layers were identified by TEM and EDX, which could be induced by galvanic cell reaction.
Effect of Inter-die Adhesive Profile on the Integrity of Die Surface in Die Stacking Package
C. C. Flores1, F. B. Aspera2, (1)Intel Technology Philippines, Inc., Cavite, Philippines, (2)Intel Technology Philippines, Cavite, Philippines
As the number of dice stacked within a microelectronic package increases, the need to maintain die surface integrity also increases. In this paper, one assembly-related rootcause mechanism causing passivation-metal damage (PMD) will be featured. The profile of inter-die adhesive was found to play an important role to maintain the integrity of die surface as more dice are being stacked in a microelectronic package. Recommended solution to prevent this type of failure will be discussed also.
Effect of Die Chip-outs and Reflow Temperature on the Mechanical Behavior of a 5-Die-Stacked Chip Scale Package
D. E. L. Balacano, L. P. De La Rama, Intel Technology Philippines, Inc., Gen. Trias, Cavite, Philippines
During package qualification, a 5-die-stacked chip scale package was being marginally triggered on high stand-by current collectively known as Power ICCS failure. Affected lots are subjected to 3x reflow at 240ºC. Post reflow failures include blown_up, high standby current in Vcc pin (ISBLO), and high standby current in Vccq pin (ISBLOQ). Backside chip-outs are observed on Die 1 and Die 3 of the three failures. Electrical validation showed that only Die 3 is failing. Corner crack on Die 3 is common to the blown_up and ISBLO failing units while crack on Die 3 backside is observed to propagate toward the active area on ISBLOQ failing units. Fracture analysis results show that the crack of the three failures all originated from die backside chip-out. Thermo-mechanical model of the package shows that, by design, Die 3 generates the highest stress concentration. Results show that if chip-outs are present on the area of the die with the highest stress concentration and the unit is subjected to reflow temperature of 240ºC, die crack will propagate from the chip-out. This paper presents the unique failure mechanism observed on a 5-die-stacked chip scale package and the corrective actions applied to solve the issue.
Study of FBGA Burn Failure under THB Test
J. Zhou, W. Zheng, M. Lou, T. Lee, Samsung Semiconductor China R&D Co. Ltd., Suzhou, Jiangsu Province, China
Temperature humidity bias (THB) test is widely used to evaluate the moisture resistance of non-hermetic packages in semiconductor industry. During THB test, one kind of 90FBGA was found severely burned and the evidence has been completely destroyed. This brings a great challenge to failure analysis. In this paper, a double daisy chain structure substrate was designed to reproduce the short and burn failure. The substrate layout design, bias and high humidity environment were proved to be the three key factors inducing dendrite grown and burn failure. A “corner-missing” phenomenon inspected through nano-focus X-ray was reported and it could finely verify the theory of electrochemical migration. The countermeasure to prevent burn failure was proposed for the designers. The insulation property degradation due to THB test was evaluated.
Study of a Systematic Low DPPM Reliability Defect Without Common Electrical Signature
F. Zhang, Texas Instruments Inc., Dallas, TX
Possible reliability failure mechanisms on mixed-signal IC are reviewed and categorized. Based on the nature of reliability and low DPPM failures on mixed signal IC, an analysis flow is proposed including identification of individual failure mechanisms, extraction of the systematic problems, and implementation of corrective actions. Finally, a case of successful isolation of a specific defect without common electrical signature on mixed-signal devices is presented.
Laser Assisted Lock-in Phase & Spectral Analysis Techniques at Advanced IC Failure Analysis with Application to Jitter and Soft-Defects
C. Brillert, Z. Qian, C. Burmer, Infineon Technologies AG, Munich, Germany
New developments concerning lock-in phase and an advanced spectral analysis technique applied to accessible IC signals is introduced in detail. The techniques combine the thermal laser stimulation (TLS) with high sensitivity of lock-in technique or frequency spectrum analyzer to phase signal. The difference to other lock-in techniques utilizing pulsed lasers is exemplary pointed out. Moreover the application to phase related soft-defects and to a design related jitter problem is shown. The power of such techniques for direct mapping a phase jitter path is shown. Further benefits of lock-in phase methodology and spectral analysis technique applied to 65 nm and 90 nm technology is presented and illustrated using different case studies.
Localization of Cu/Low-K Interconnect Reliability Defects by Pulsed Laser Induced Technique
A. C. T. Quah1, T. L. Tan2, C. L. Gan3, J. C. H. Phang4, C. M. Chua5, C. M. Ng6, A. -. Y. Du7, (1)National University of Singapore, Singapore, Singapore, (2)Nanyang Technological University, Singapore, Singapore, Singapore, (3)Nanyang Technological University, Singapore, Singapore, Singapore, (4)Centre for Integrated Circuit Failure Analysis and Reliability (CICFAR), National University of Singapore, Singapore, Singapore, (5)SEMICAPS PTE LTD, Singapore, Singapore, Singapore, (6)Chartered Semiconductor Manufacturing Ltd, Singapore, Singapore, (7)Institute of Microelectronics, Singapore, Singapore
In this paper, the application of pulsed-TIVA for the localization of Cu/low-k interconnect reliability defects will be described. It will be shown that subtle dielectric defects which are otherwise not detectable with conventional TIVA can be detected with pulsed-TIVA.
Ultra Low Voltage Probing on 45 nm CMOS by Time Resolved Emission (TRE) Technology
C. L. (. Young, Intel Corporation, Santa Clara, CA
Ultra low voltage probing by TRE technology below 1.0V is very challenging for Micro-processor debug in practical operation condition. This is because the photo-emission rate reduces exponentially as the power supply voltage (Vcc) decreases. In this paper, a new technology with improved detector in Solid Immersion Lens (SIL) TRE system was demonstrated for low voltage and small node probing. This technology improves the photon collection efficiency and lowers the dark noise to 8 KHz with advance InP/InGaAs Avalanche Photo Diode (APD). The performance gain of acquisition time reduction was shown on 45nm CMOS processor with the capability of 0.75V probing.
Masking Technique to Enable Multiple Site Defect Analysis on a Microchip
J. C. Hahn, Altera Corp., San Jose, CA
Conventional deprocessing (or delayering) techniques ('parallel lapping' or 'polishing') can only maintain planarity over a small area (a few tens of microns). Analysis is restricted to a small area, or if analysis on multiple sites is required, one would typically have to perform several iterations of deprocessing. This PFA technique eliminates or reduces the need of committing the sample to repeated deprocessing steps, thus saving time and resources.
The Ion Beam Imaging Methodology of Invisible Metal Under Insulator Using High Energy Electron Beam Charging
C. H. Wang, S. P. Chang, C. F. Chang, J. Y. Chiou, Taiwan Semiconductor Manufacture Company, Ltd., Taiwan, Tainan, Taiwan
On advanced technology, we often need to use focused ion beam to modify the circuit for new layout verification or electrical measurement. We prepare the sample till inter-metal dielectric (IMD), then dig the hole or deposit the metal, oxide by ion beam. We all know we can’t see the metal under oxide by ion beam but we must get the metal ion imaging we want, and then do the further action. By the advantage of dual beams, we find the phenomenon when switching ion and electron beam. The phenomenon can make the invisible metal show up. The detail will be demonstrated below.
A Case Study of Defects Due to Process-Design Interaction in Nano Scale Technology
H. S. Lin, UMC, Hsin-Chu City, Taiwan
The difficulties in identifying the precise defect location and real leakage path is increasing as the integrated circuit design and process have been becoming more and more complicated in nano scale technology node. Most of the defects causing chip leakage are detectable with only one of the FA tools such as LCD (Liquid Crystal Detection) or PEM (Photon Emission). However, some defects due to marginality of process-design interaction are often not detectable with only single FA tool. We show an example of process-design related defect which only could be detected with more advanced FA tools.
STI Punch-Through Degradation Related Standby Current Failure in HTOL Test-A-Case Study
W. R. Chen, L. K. Kuo, Macronix International Co., Ltd., Hsin-chu, Taiwan
This report summarizes the analysis results of 0.13µm technology 256Mbits NBit HTOL induced standby current failures caused by STI(Shallow Trench Isolation) punch through induced leakage degradation. Electrical analysis, EMMI and stress experiment on test devices are employed to identify the failure mechanisms, root causes, and corrective solutions. From this study, improvements could be achieved by circuit layout modification.
Bevel Etching: A Low Cost Alternative fo FIB
B. Seidl, J. Walter, M. Kirchberger, Infineon Technologies AG, Regensburg, Germany
The aim of the presented poster is to introduce a time and cost efficient preparation technique for FESEM investigations with focus on typical issues in electronic packaging development and failure analysis. The new ion beam based technique acts as a low cost alternative to FIB, able to prepare much wider section areas, combined in a tool, which can also be used for standard ion beam polishing processes.
Evaluation of Cross-Sectional Sample Preparation Techniques for 2D Doping Profiling of Specific Site by SCM
T. K. Lee, T. S. Back, J. H. Kim, Y. B. Park, H. J. Kim, S. Y. Lee, Hynix Semiconductor Inc, Icheon-si, South Korea
In this study, we demonstrated and evaluated that micro-cleaving and FIB milling are applicable to prepare cross-sectional sample of specific site for SCM observation. It is found that both techniques show good SCM results and are applicable to preparing cross-sectional sample of specific site for SCM investigation.
The Failure Site Localization Using Absorbed Electron Image and Voltage Distribution Contrast
T. Nokuo1, Y. Eto1, Z. Marek2, (1)JEOL Ltd., Akishima Tokyo, Japan, (2)JEOL USA, Inc., Peabody, MA
In semiconductor failure analysis, a detection of abnormal resistive site is required for localization of failure site in interconnects. Authors have developed an instrument, which is able to detect abnormal resistive site using absorbed electron image (AEI) and voltage distribution contrast (VDIC) by combining a SEM and nano-probing technique [1]. In this paper, the abilities for abnormal resistive site detection of AEI and VDIC are evaluated and reported.
A Simple Adapter for Soft Defect Localization using OBIRCH
T. Kolasa, Superior Technical Services, Scottsdale, AZ
This paper presents details of a simple adapter that was developed to add SDL capability to our OBIRCH tool. Examples of results are also presented.
Integrated Raman - IR Thermography for Reliability and Performance Optimization, and Failure Analysis of Electronic Devices
M. Kuball1, A. Sarua1, J. W. Pomeroy1, A. Falk2, G. Albright3, M. J. Uren4, T. Martin4, (1)University of Bristol, Bristol, United Kingdom, (2)OptoMetrix, Inc, Renton, WA, (3)Quantum Focus Instruments, Vista, CA, (4)QinetiQ, Malvern, United Kingdom
We report on the development of a novel thermography technique, integrated Raman – IR thermography, illustrated here on AlGaN/GaN electronic devices. As it is a generic technique future application to Si, GaAs and other devices is anticipated. While IR thermography can provide fast temperature overviews, its current use for many of todays’ technologies is complicated by the fact that it does not provide the spatial resolution needed to probe sub-micron/micron size active device areas. Integrating IR with micro-Raman thermography, providing temperature information with 0.5 micrometer spatial resolution, enables unique thermal analysis of semiconductor devices to a level not possible before. This opens new opportunities for performance and reliability optimization, and failure analysis of electronic and other devices.
Reduction of Acquisition Time for RIL, SDL and LADA
A. Mels, F. Zachariasse, NXP Semiconductors, Nijmegen, Netherlands
Starting from the concept of the shmoo edge as a smooth transition from 100% fail to 100% pass, we have developed a model of LADA signal strength. By combining this model with a suitable measure for image quality, we derived equations for the acquisition time needed to discern a LADA response from the background noise. Comparison of the model to experimental data shows that it is indeed a realistic representation. For weak signals, we show that the optimal condition, for minimum acquisition time, is at the 50% pass/fail point of the shmoo plot. Under these conditions, the acquisition time decreases quadratically with an increase in laser-induced timing shift, or a decrease in jitter. We investigated a number of ways to improve the LADA response. Performing LADA at reduced supply voltages appears to be a promising avenue to achieve this. In some device types, it results in a 7-fold reduction in acquisition time. In conclusion the model offers a quantitative tool to estimate the feasibility of a given LADA measurement and a guide to optimising the required experimental set-up.
A New Approach for SRAM Soft Defect Root cause Identification
P. Egger, S. Müller, M. Stiftinger, Infineon Technologies AG, Munich, Germany
With shrinking feature size of integrated circuits traditional FA techniques like SEM inspection of top down delayered devices or cross sectioning often cannot visualize the physical root cause anymore. Especially inside SRAM blocks with their aggressive design rules a shift of transistor parameter can cause a local mismatch and therefore a soft fail of a single SRAM cell. This paper will present a new approach to identify a physical root cause with the help of nano probing and TCAD simulation and allows the wafer fab to implement countermeasures.
3D Defect Localization by Measuring and Modeling the Dynamics of Heat Transport in Deep Sub-Micron Devices
A. Reverdy1, M. De La Bardonnie2, M. Lamy3, L. F. T. Kwakman4, C. Wyon5, H. Murray6, P. Perdu7, (1)NXP Semiconductors, Caen, France, (2)NXP Semiconductors, Crolles, France, (3)STMicroelectronics, Crolles, France, (4)FEI Company, Eindhoven, Netherlands, (5)CEA-LETI, Grenoble, France, (6)LaMIP, Caen, France, (7)CNES - French Space Agency, Toulouse, France
In our aim to improve the TLS based fault isolation method, we have studied thermal time-constant signatures using Dynamic Optical Beam Induced Resistance Change (D-OBIRCH), that may provide z-information of defects in the metallization part of devices (BEOL).
Real-Time FTIR Etch Depth Measurements in Passive Integrated Silicon Substrates
F. Roullier1, B. Domengès2, J. P. Blanvillain1, (1)NXP Semiconductors, Caen, France, (2)CNRT-CNRS, Caen, France
This paper deals with real-time FTIR etch depth measurements performed on passive integrated silicon substrates. High-density trench capacitors are non-destructively characterized using FTIR Michelson type spectrometer. Based on effective medium approximations, an effective index associated to the capacitor layer is introduced which allow a good evaluation of the capacitor hole depth. Obtained results correlate well with those from SEM measurements performed on cross-sections, on a range going from 12µm to 30µm depth.
Blind Deconvolution of SEM Images
W. E. Vanderlinde1, J. Caron2, (1)Laboratory for Physical Sciences, College Park, MD, (2)Research Support Instruments, Lanham, MD
In this paper we demonstrate that an image processing technique called blind deconvolution is able to improve the ultimate resolution of a scanning electron microscope by 40%. However, requirements on image bit depth and signal to noise present significant difficulties to using the technique on a routine basis.
Nondestructive Defect Imaging through Image Intensity Analysis
J. J. Demarest1, A. Dalton2, L. Hahn3, B. Redder3, F. Wallingford3, D. Bearup4, (1)IBM, Albany, NY, (2)IBM Systems & Technology, Hopewell Junction, NY, (3)IBM, Hopewell Junction, NY, (4)Clarkson University, Potsdam, NY
Due to shrinking dimensions in semiconductor technology (65 nm and smaller) it is now possible to use an electron beam as a materials sensor making it possible to image subsurface voids due to less electron signal when compared to a reference site. As a consequence a 3D representation of a subsurface void can be obtained prior to cross sectioning.
Automated TEM Sample Preparation on Wafer Level for Meterology and Process control
B. Rijpers1, D. Verkleij2, E. Langer3, (1)ASML, Veldhoven, Netherlands, (2)FEI, Eindhoven, Netherlands, (3)GLOBALFOUNDRIES, Dresden, Germany
Using TEM for process control is a challenge because a high level of automation is needed to be able to gather statistically valid cross section metrology data with short cycle times. We have developed a method to do this for both photoresist and etched gates and we will show the roadmap towards TEM based statistically valid process control (APC).
Applications of Electron Tomography on Advanced DRAM
J. S. Luo, J. D. Russell, L. Y. Huang, T. P. Chen, Inotera Memories, Inc., Taoyuan, Taiwan
This abstract demonstrates the technique of TEM tomography on real FA cases in DRAM technology
Studies of Galvanic Corrosion (Al-Ti Cell) on Microchip Al Bondpads and Elimination Solutions
Y. N. Hua1, S. P. Zhao2, A. Trigg3, (1)GLOBALFOUNDRIES Singapore Pte Ltd, Singapore, Singapore, (2)Chartered Semiconductor Mfg Ltd., Singapore, Singapore, (3)Institute of Microelectronics, Singapore, Singapore
In this paper, a concept and theoretical model of galvanic corrosion (Al-Ti cell) will be proposed originally, which can help us to understand physically & chemically mechanism of galvanic corrosion at bondpad edge, and allow us to eliminate it to reduce NSOP (non-stick on pads) issue at assembly processes
Construction of a 3-D Current Path using Magnetic Current Imaging
F. S. Felt, NASA Goddard Space Flight Center, Greenbelt, MD
Magnetic current imaging was performed on orthogonal sides of a rectangular 3D module encapsulating eight vertically-stacked EEPROM devices; successfully tracing current inside the module and identifying the fault location.
Investigation of Bond-Pad Etching Chemistries for Determination of Probe/Bonding Related Sub-pad Cracks
V. Korchnoy, Intel Israel (74) Ltd, Haifa, Israel
Bond-pad integrity directly affects the performance of microelectronic devices. Bond-pad cracking and related to it under-pad cracking of Inter-Metal Dielectric (IMD) may bring a high reliability risk and cause units to fail at environmental stress. Bond pad cracks could be initiated by probing during wafer sort and at wire bonding process during assembly. This paper presents the comparative analysis of the different chemistries used for exposure and decoration of pad cracks. The device was fabricated with 0.18 ƒÝm CMOS technology, has aluminum/TiN bond pads and gold wire bonds. Four different chemistries have been tried: Ferric Cyanide; Tri-iodine; Aqua Regia; hot Phosphoric acid. The investigation results showed that Tri-iodine etchant provides clean and artifact-free exposure of TiN barrier layer of the pad and is the best (from the tried methods) for pad cracks observation
Analog Building Blocks: Circuits and Devices
D. Sargent, Analog Devices Inc., Cambridge, MA
Diagnosing Analog Circuits
J. Guravage, S. Swieck, Analog Devices, Wilmington, MA
Failure Analysis of DRAM Memory
M. Versen1, S. Hoch2, (1)University of Applied Sciences Rosenheim, Rosenheim, Germany, (2)Qimonda AG, Neubiberg, Germany
CMOS Electronics and Defect Analysis
C. Hawkins, University of New Mexico, Albuquerque, NM
Failure Analysis of SRAM Memory
S. Gunturi, Texas Instruments, Inc., Dallas, TX
Flash Memory Failure Analysis
P. Vuggina, Intel Corporation, CA, CA
Emerging Trends in Failure Modes of Nanotechnology
T. Kane, IBM, Hopewell Junction, NY
Electrical Overstress (EOS) in Semiconductor Devices: How to Differentiate and Document EOS due to Over-Current or Over-Voltage Conditions
C. Lewis, T. Simons, Texas Instruments, Dallas, TX
ESD Testing of Electronic Components using the Transmission Line Pulse Methodology
L. G. Henry, ESD-TLP Consulting & Testing, Fremont,, CA
Failure Analysis Flow Decision Tree
C. Richardson1, K. S. Wills2, (1)Abound Solar, Fort Collins, CO, (2)Independent Consultant, Sugar Land, TX
Classic Case Histories
J. Colvin, FA Instruments, San Jose, CA
Delayering Techniques: Dry Processes, Wet Chemical, Parallel Lapping
K. S. Wills1, S. Perungulam2, (1)Independent Consultant, Sugar Land, TX, (2)Texas Instruments, Stafford,, TX
Electromigration in Copper Interconnects - Failure Analysis and Degradation Studies
E. Langer, GLOBALFOUNDRIES, Dresden, Germany
Lock-in Thermography
O. Breitenstein, Max Planck Institute of Microstructure Physics, Halle, Germany
Flip-Chip and Backside Analysis Techniques
E. I. Cole Jr.1, D. L. Barton2, K. Bernhard-Höfer3, (1)Sandia National laboratories, Albuquerque, NM, (2)Sandia National Laboratories, Albuquerque, NM, (3)Infineon, Munich, Germany
Photonic Localization Techniques
C. Boit, TUB Berlin University of Technology, Berlin, Germany
The Role of the AFM in Yield and Failure Analysis
J. Colvin, FA Instruments, San Jose, CA
The Pivotal Role of AFP Nanoscale Failure Analysis
R. E. Mulder, Silicon Labs, Austin, TX
Beam-Based Defect Localization Techniques
E. I. Cole Jr., Sandia National laboratories, Albuquerque, NM
Fundamentals of Laser Based FA Techniques
R. A. Falk, Quantum Focus Instruments, Tukwila, WA
FIB – A Design Repair / Fault Isolation Tool
S. Herschbein1, C. Richardson2, (1)IBM Systems & Technology, Hopewell Junction, NY, (2)Abound Solar, Fort Collins, CO
Focused Ion Beam — a Sample Preparation Tool
K. Hooghan, Hooghan Consultancy and Services, Murphy, TX
Failure Localization with Active and Passive Voltage Contrast in FIB and SEM
R. Rosenkranz1, J. Tejero2, W. Werner1, (1)Qimonda Dresden GmbH & Co. OHG, Dresden, Germany, (2)Qimonda Dresden GmbH & Co. OHG, Dresden, CO, Germany
Cost of FA and Debug
S. P. Maher, Oklahoma Christian University, Oklahoma City, OK
Failure Analysis Lab Management Overview
R. Ross, Independent, VT
Lead Free Challenges
V. S. Vasudevan, Intel Corporation, Hillsboro, OR
Materials Characterization for Failure Analysis
T. A. Anderson, ON Semiconductor, Phoenix, AZ
Materials Characterization - Surface Analysis in Assembly
A. Proctor, Intel Corporation, Chandler, AZ
Introduction to Microelectromechanical Systems (MEMS) Materials and Fabrication Processes
J. A. Walraven, Sandia National Labs, Albuquerque, NM
Introduction to and Reliability in MEMS Packaging
T. R. Hsu, San José State University, San José, CA
Optoelectronic Techniques for MEMS and Electronic Packaging Characterization
C. Furlong, Worcester Polytechnic Institute, WPI, Worcester, MA
Optical and Infrared FA Microscopy
J. J. McDonald, Quantum Focus Instruments Corporation, Vista, CA
Scanning Electron Microscopy
W. E. Vanderlinde, Laboratory for Physical Sciences, College Park, MD
Transmission Electron Microscopy for Failure Analysis
S. Subramanian, Freescale Semiconductor, Inc., Austin, TX
Advanced Techniques in Sample Preparation and TEM Analysis of Microelectronic Materials
R. R. Cerchiara1, P. E. Fischione1, J. J. Gronsky2, A. C. Robins1, K. L. Tichenor2, (1)E.A. Fischione Instruments, Inc., Export, PA, (2)E. A. Fischione Instruments, Inc., Export, PA
Ultra-High Resolution Scanning Electron Microscopy
W. E. Vanderlinde, Laboratory for Physical Sciences, College Park, MD
Enhanced De-Packaging and Chip Access FA Techniques
O. Diaz de Leon, Texas Instruments, Stafford, TX
Chip Scale Package and Its Failure Analysis Challenges
S. Li, Spansion Inc, Sunnyvale, CA
Repackaging
R. D. Harrison1, S. Wills2, (1)Texas Instruments, Dallas, TX, (2)Independent Consultant, Sugar Land, TX
X-Ray & SAM Challenges for IC Package Inspection
T. M. Moore, Omniprobe, Inc., Dallas, TX
Time Domain Reflectometry
D. Smolyansky, TDA Systems, Lake Oswego, OR
Magnetic Based Current Imaging for Fault Isolation in Die and Packages
L. A. Knauss, Booz Allen Hamilton, Annapolis Junction, MD
From Scan Testing to Embedded Testing
M. Keim, Mentor Graphics, Wilsonville, OR
Defect-Oriented Testing
R. Aitken1, A. Gattiker2, (1)Artisan Components, Sunnyvale, CA, (2)IBM Corporation, Austin, TX
Logic Diagnostics: Techniques, Applications and Challenges
S. Venkataraman, Intel Corporation, Hillsboro, OR
FA Case Histories using ATPG and SCAN Diagnostics
K. S. Wills, Independent Consultant, Sugar Land, TX
Yield Basics for Failure Analysis including 300mm wafer and Cu Technology
T. Myers, ON Semiconductor, Gresham, OR