Novel Sample Preparation Technique for Backside Analysis of Singulated Die
S. M. Elliott, M. R. LaPierre, P. R. Plourde, Fairchild Semiconductor, South Portland, ME
Backside techniques to isolate faults in integrated circuits are a common approach used by many failure analysts, and the increasing number of metallization layers of many semiconductor devices today makes backside analysis necessary. Traditionally, backside analysis involves parallel polishing the back of the package and/or die to thin and expose the die substrate. The sample is then biased in the failing mode using inverted microprobes or open socketed test board in the analytical tool of choice and near-infrared (NIR) imaging is performed. One challenge facing failure analysts today is the continuously shrinking dimensions of semiconductor devices. Semiconductor device packages are approaching the dimensions of the singulated die, as evidenced by the increasing popularity of chip scale packages (CSP). CSP devices integrate the semiconductor die and connecting leads consisting of BGA (Ball Grid Array) or LGA (Land Grid Array) into a compact footprint within the size of the semiconductor die itself. Because of this, existing backside analysis techniques on CSP devices or singulated die is not feasible since no “package” exists to secure and mount the sample during inverted electrical testing without obscuring the active area of the die during NIR imaging. This paper discusses a novel and cost effective approach to perform backside analysis on a singulated die or CSP device.
The failure analysis of specific source-to-drain dislocation and case study
C. H. Wang, S. W. Lai, C. Y. Wu, B. T. Chen, J. Y. Chiou, J. H. Chou, Taiwan Semiconductor Manufacture Company, Ltd., Taiwan, Tainan, Taiwan
Many process parameters affect the device behaviour and cause the front-end defect. Simply, the failure are two types: high-resistance and leakage, especially the leakage mode defect is difficult to inspect. Although conductive atomic force microscopy and six probes nano-probing are popular tools for front-end failure inspection, some specific defects still need more effort. We will demonstrate the electrical phenomenon and analysis of crystalline defect.
Next Generation Laser Voltage Probing
Y. S. Ng1, W. K. Lo1, K. R. Wilsher1, F. Beaudoin2, (1)DCG Systems, Fremont, CA, (2)IBM
Presentation on Next Generation of Laser Voltage Probing
A study of photoelectric effect caused by laser beam used for beam bounce technique in a C-AFM system
H. S. Lin, M. S. Wu, UMC, Hsin-Chu City, Taiwan
The use of the scanning probe microscope (SPM) such as conductive atomic force microscope (C-AFM) has been widely reported for failure analysis of nano-meter scale science and technology [1-6]. A beam bounce technique is usually used to enable the probe head to measure extremely small movements of the cantilever as it is moved across the surface of the sample. However, the laser beam used for the beam bounce also gives rise to the photoelectric effect while we are measuring electrical characteristics of a device such as a pn junction. In this paper, the photocurrent for a 90nm node device caused by photon illumination was quantitatively evaluated. In addition, this paper also present an example of an application of C-AFM as a tool for failure analysis of trap defects by taking advantage of the photoelectric effect.
Applications of C-AFM and CBED techniques to the characterization of substrate dislocations causing SRAM soft single column failure contained in a wafer with (001) plane/[100] notch
H. S. Lin, T. H. Chen, W. C. Shu, UMC, Hsin-Chu City, Taiwan
It has been long recognized that SRAM memory is an ideal vehicle for defect monitoring and yield improvement during process development because of its highly structured architecture and simplified approach by memory bitmapping. However, the success rate of defect detection, especially for soft single column failure which is one of the most complex failure modes of an SRAM failure, is decreasing by traditional standard PFA with only the bit map available for guidance due to a variety of invisible or undetectable defects causing leakage behavior in the device. In order to understand the leakage behavior in advanced high voltage (HV) process, Conductive Atomic Force Microscope (C-AFM) [1-3] is introduced to perform junction level fault isolation prior to attempting physical failure analysis (PFA). According to J. P. Morniroli, crystalline defects affect convergent-beam electron diffraction (CBED) and large angle convergent-beam electron diffraction (LACBED) patterns, so CBED and LACBED techniques were also applied to the specimens containing dislocations for further characterization of these defects [4]. In this study, the quantified data extracted by C-AFM can also be used to build up a connection between a failure mechanism discovered and the soft single column failure mode.
Electroluminescence analysis by precise tilt polish technique of edge-emitting laser diode
H. Ichikawa1, K. Sasaki1, K. Hamada1, A. Yamaguchi2, (1)Sumitomo Electric Industries, LTD, Yokohama, Japan, (2)Sumitomo Electric Industries, LTD, Itami, Japan
We employed in development of EL analysis that was used for failure analysis of edge-emitting LD. To extract EL emission from an LD, we developed tilt polish technique of bottom electrode. Then we successfully observed clear EL emission. Though severe control was required, high yield of 99.2 % was achieved by introduction of precise tilt polish technique.
A Novel OBIRCH Failure Localization for Leakage fail in Flash Product Failure Analysis
C. L. Huang, Y. H. Shu, United Microelectronics Corporation, Ltd., Hsinchu, Taiwan
Conventional localization techniques such as Optical Beam Induced Resistance Change (OBIRCH) or photoemission microscopy (EMMI) sometimes fail when applied to power semiconductor devices. In this paper, We present a novel FA technique for failure localization. It is a powerful failure localization technique, where using a novel method in OBIRCH system is utilized to find hot spot. We will focus on this hot spot to do detail electrical analysis which includes Conductive Atomic Microscopy (C-AFM) and nano-probing . Finally, the failure mechanism was illustrated with nano-prober and Cross-Section TEM.
Case study of high temperature failure analyses using an on-chip “heater”
F. Zhang1, C. Lewis2, T. Duryea1, (1)Texas Instruments Inc., Dallas, TX, (2)Texas Instruments, Dallas, TX
Two cases of high temperature failure analyses are presented. In both cases an on-chip “heater” – power MOSFET was used to achieve high temperature for global fault isolation or block/transistor level nodal analysis. The “heater” provides a quick way of changing the device temperature without significantly modifying the bench setup. In both cases, the results show improved probability of successfully isolating the fail site, by performing OBIRCH analysis and nodal analysis.
Development of PECS Application for Sample Preparation
X. F. F. Chen, M. Li, Q. Guo, K. Chien, Semicoductor Manufacturing International Co., Shanghai, China
In this work, Ar plasma etching by PECS system was developed to replace time-consuming fainal polishing. And experiment was designed to optimize gun parameters for removing different kinds of artifact induced by polishing.
Automated Sample Preparation of Packaged Microelectronics for FESEM
R. R. Cerchiara, P. E. Fischione, M. F. Boccabella, A. C. Robins, E.A. Fischione Instruments, Inc., Export, PA
Automated sample preparation of packaged devices is done using a combination of mechanical, ion and plasma based techniques.
Studies of fluorine-induced corrosion and defects on microchip Al bondpads and elimination solutions
Y. N. Hua1, J. Teong2, (1)GLOBALFOUNDRIES Singapore Pte Ltd, Singapore, Singapore, (2)Chartered Semiconductor Manufacturing Ltd, Singapore, Singapore
In wafer fabrication (fab), CF4 gas is used for Al bondpad opening process. Thus, on a normal Al bondpad, there is a low level of fluorine (F) contamination, which could not cause F-induced corrosion & defects. However, if F contamination is higher than baseline to certain level on Al bondpads, it may cause F-induced corrosion on microchip Al bondpads, which may result in bondpad discoloration or non-stick on pads (NSOP). In authors’ previous studies [Hua et al, ISTFA 2002 and ISTFA 2003], theory, characteristics and eliminating solutions of Fluorine-induced corrosion have been studied. In this paper, we will further study failure mechanism of F-induced corrosion defects on Al bondpads and introduce a concept of Al fluoride oxide (AlxOyFz) defect besides Al fluoride ([AlFx](x-3)-) defect. Theoretical model of Al fluoride oxide (AlxOyFz ) will be proposed to explain chemically & physically mechanism of fluorine-induced corrosion on Al bondpads and three kinds of Al fluoride oxide defects (crystal-like, oxide-like and cloud-like) will be discussed. According to theoretical models proposed in this paper, F will chemically react with Al and form Al fluoride ([AlFx](x-3)-). It is a chemically stable compound and does not dissolve in water. Therefore, once it is formed, it will be difficult to be cleaned away using a normal wafer fab cleaning process. Moreover, O2 & H2O (moisture) will enhance F corrosion and cause chemical reactions to generate OH- ions, which will further chemically react with Al to form Al hydroxide, Al(OH)3 and Al oxide (Al2O3), and then form Al fluoride oxide (AlxOyFz). All these F-induced corrosion defects will cause bondpad discoloration & NSOP problem. In this paper, failure analysis methodologies & eliminating solutions of F-induced corrosion and controlling/monitoring program will be also discussed.
Optimization of SEM analytical conditions for low K and ultra low K dielectric materials
B. H. Liu1, Z. Q. Mo2, Y. N. Hua3, (1)Chartered Semiconductor Mfg Ltd, Singapore, Singapore, (2)Chartered Semiconductor Manufacturing Ltd., Singapore, Singapore, (3)GLOBALFOUNDRIES Singapore Pte Ltd, Singapore, Singapore
The electron beam induced radiation damage presents great challenges for the electron microscopy analysis of low k and ultra low k dielectrics due to their beam sensitive nature. In order to minimize the radiation damage, it is necessary to understand the mechanisms. This work presents detailed studies regarding the mechanisms behind the effects of probe currents, accelerating voltage and anti-charging coating layers on the radiation damage to low/ultra-low K dielectrics. The results indicate that the probe current shows a stronger dependence on the size of the condenser lens aperture than the accelerating voltage. Therefore, in terms of the probe current, condenser lens aperture plays a decisive role in affecting the radiation damage process. In order to minimize the radiation damage, the SEM imaging should be conducted with not only a low accelerating voltage but also a small condenser lens aperture to reduce probe current. Based on simulation results, the effects of coating layer and accelerating voltage are related to the interaction volume and the penetration depth of electron beam. Pt coating can act as not only an anti-charging layer, but also an effective barrier layer for reducing electron flux that entering in the low/ultra-low dielectrics.
Using cross-triggering in oscilloscope for debugging multiphase converter circuit of Personal Computer (PC) motherboard
B. T. Nguyen, O. Diaz, Intel Corporation, Hillsboro, OR
Summary: Analyzing failure on multiphase converter circuit on PC motherboards presents significant challenges due to the high number of nodes and the timing relationship between them. Typically a standard 4-channel oscilloscope cannot capture the necessary timing relationships to effectively analyze the whole circuit. There are two test points for each phase of converter circuit. Typically, there are only four channels for the oscilloscope which are not enough to track the activity of 3 phases or more of converter circuit of PC motherboard. Cross-triggering is a typical feature on most oscilloscopes allows users to link two or more oscilloscopes to increase to eight channels or more. The cross-triggering metrology will make the task of doing fault isolation in multiphase converter circuit much easier and faster.
Doping Profile Measurements in a 65-nm Commercial Product using Atom Probe Tomography
L. Klibanov1, D. James1, D. Isheim2, (1)Chipworks, Ottawa, ON, Canada, (2)Northwestern University Center for Atom-Probe Tomography (NUCAPT), Evanston, IL
Failure Analysis of Nitride-Trapping Memory Cell Failures
W. R. Chen, Y. J. Chen, Macronix International Co., Ltd., Hsin-chu, Taiwan
The 2-bit/cell nitride-trapping device (NROM/Nbit) is one of the important type of NVM (Non-Volatile Memory) devices and is a potential candidate for replacing FG-type NVM device below 45nm node. In this study, electrical and physical failure analyses were used and the failure mechanisms and root causes of the testing vehicle devices fabricated by 130nm NBit technology were determined. Because cell dimension and spacing requirements for high-density memory are quite aggressive, these observations help to optimize process and improve yield.
Advanced Methodologies for Backside Circuit Edit
T. Malik1, R. Jain1, T. Lundquist2, (1)DCG Systems Inc., Fremont, CA, (2)DCG Systems, Fremont, CA
Contacting signals inside an integrated circuit (IC) is critical to debug new devices. Current flip chip circuit edit techniques are limited to spot resolution and chemistry constrains of the Focused Ion Beam (FIB) system. The new proposed technique uses a FIB circuit edit tool to contact signals at transistor level. The device is prepared using global silicon thinning and polishing tool with low risk of device performance degradation.
Physical Failure Analysis Techniques using 3D Rotation Imaging Method by STEM
T. S. Back, J. H. Kim, S. J. Lee, J. W. Jung, T. O. Jung, H. J. Kim, J. H. Lee, Hynix Semiconductor Inc, Icheon-si, South Korea
In recently, many difficult failures are appeared by cross sectional TEM image of only specific site. Defects were found when the SOD and HDP filled in the gap of STI according to volume expansion of SOD film. The expansion causes the increased tensile stress of the film, and this makes crystalline defects which can be found in shape of multi shared column fail in the sense amp regulating bit lines. In this paper, we introduce the electrical method of analyzing the cause of these problems. Using a common method, Cross-section analysis by FIB TEM, we inspected the dislocation. When it comes to the difficult to analyze, we made a pillar type of specimens by utilizing a 3D rotation holder. Then, the specimens were totally analyzed with the Rotation Imaging Method.
High Precision Ion Beam Milling with Time of Flight Compensation
T. Holtermann, M. DiBattista, S. Rosenberg, A. Graupera, FEI Company, Hillsboro, OR
For optimal control in circuit edit processing, Time of Flight compensation in the ion column deflection system increases the beam placement accuracy and patterning accuracy in advanced circuit edit applications.
Applications of in-situ sample preparation and modeling of SEM-STEM imaging
R. J. Young1, A. Buxbaum2, B. Peterson1, R. Schampers3, (1)FEI Company, Hillsboro, OR, (2)FEI, Hillsboro, OR, (3)FEI Company, 5600 KA Eindhoven, Netherlands
Using STEM mode in a DualBeam FIB-Sem system offers benefits for both sample preparation and for high resolution imaging. This paper covers modeling of STEM contrast in such as system and describes how this can be applied to improve image interpretation and sample preparation.
Sample Preparation Technique for Bond Pad Oxide Damage Observation
Y. L. Kuo, Y. S. Huan, Y. T. Lin, J. Chen, K. Y. Lee, Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, Taiwan
This paper is discussing a methodology to reveal real defect of oxide crack that cannot be seen on the bond pad with minimum FA artifact.
Dynamic Laser Stimulation technique for device qualification process
A. DEYINE-BARTH, CNES, IMS, Toulouse, France
Forecast the duration while a device will be able to perform its task is a key point for some application. The aim of this paper is to present how to save time having accurate results sooner in device qualification process, using a failure analysis technique, such as Dynamic Laser Stimulation, to detect marginalities in operating parameters
Lead frame metal migration in an encapsulated IC package
W. E. Eslinger, Boston Scientific, St. Paul, MN
This case study details a latent IC (integrated circuit) failure mechanism caused by migration of silver (Ag) inside the encapsulated package of a CMOS (complementary metal-oxide-silicon) device. The source of the migrated silver was the plating of the lead frame and metallic ‘stringers’ were deposited at the material interface between the die attach epoxy and the plastic encapsulate. The migrated metal created fragile electrical connections between adjacent lead frame legs, over distances greater than 150 µm.
Latent Flash Single Bit and Multiple Bits Systematic Approach to Failure Analysis
H. Y. To1, D. T. Nguyen2, C. Dunn1, D. Davis1, (1)Texas Instruments Inc., Stafford, TX, (2)Texas Intruments, Inc., Dallas, TX
Flash failure was reported at different point after leaving the fab and at different temparature. To verify the issue, stress test was performed using voltate and temperature stress tests. The failure circuitry was determined from electrical failure analysis and test, which identified the failure in the MUX. The physical failure analysis includes voltage contrast on the circuitry involved, nanoprobing of the transistor in question, and TEM crossection at the defect location. TEM showed Cobalt/Carbon siliside residue on the sidewall.
Reliability for Pure CMOS One-time Programmable Memory Using Gate-Oxide Anti-fuse (eFuse)
N. Wakai, Toshiba Corporation, Yokohama, Japan
Reliability of our developed pure CMOS One-time Programmable (PCOP) Memory was investigated. Memory is programmed with the breakdown of the thin gate oxide. The result of reliability stress test, it is found that PCOP memory is stable and reliable for severe environmental condition.
Single Die 'Hands-Free' Layer-by-Layer Mechanical Deprocessing for Reverse Engineering
T. Moor1, E. Malyanker2, E. Raz-Moyal2, (1)Datel Electronics, Stone Staffordshire, United Kingdom, (2)Gatan Inc, Pleasanton, CA
This paper presents a technique for the full layer-by-layer deprocessing of a single semiconductor device using purely mechanical polishing for Destructive Semiconductor Reverse Engineering (DSRE). Although there are many mechanical polishers and techniques available in the market place and with an expert user can produce satisfying results, there are 2 known concerns: <100% success rate and edge effect. When an FA engineer has returned parts to investigate, or more likely, when a Reverse Engineer needs to employ existing methods to investigate a device as a whole, every sample is a one of a kind and the deprocessing must be well controlled to produce 100% success. Exposing 95% of the die in the centre, leaving out edges and corners may not be good enough. This paper will reveal the overall process flow, the process conditions, the preparation of the sample and the very important and novel changes to the process that are required to delayer a single die to such a high degree of planarity, so 100% of the die can be exposed at the same time and at the same Inter Layer Dielectric (ILD).
Characterisation and failure analysis of wafer-bonded devices and unfilled Through-Silicon-Vias (TSVs)
C. Cassidy, austriamicrosystems AG, Unterpremstaetten, Austria
This paper is concerned with characterisation and failure analysis challenges posed by 3D integration of semiconductor devices, with a particular focus on wafer bonded components and Through Silicon Vias (TSV). Advantages and limitations exhibited by various different sample preparation techniques, when applied to integrated devices, are discussed. Challenges encountered with real devices are presented, along with successful solutions enabled by a precision polishing toolset (Gatan Frontier).
Detection and Characterization of an Electrical Failure Induced during Laser Ablation of Packages
P. Schwindenhammer, NXP Semiconductors, CAEN, France
Abstract Decapsulation of complex semiconductor packages for failure analysis is enhanced by laser ablation. If lasers are potentially dangerous for Integrated Circuits (IC) surface they also generate a thermal elevation of the package during the ablation process. During measurement of this temperature it was observed another and unexpected electrical phenomenon in the IC induced by laser. It is demonstrated that this new phenomenon is not thermally induced and occurs under certain ablation conditions.
Timing failure debug using debug-oriented scan test patterns
C. Burmer1, R. Guo2, W. T. Cheng2, X. Lin2, B. Benware3, (1)Infineon Technologies AG, Munich, Germany, (2)Mentor Graphics, Wilsonville, OR, (3)Mentor Graphics, OR
We describe a silicon debug flow that uses debug-oriented scan test patterns to improve the efficiency of physical fault isolation. The debug-oriented test patterns are especially generated to meet the requirement of fault isolation using time-resolved emission (TRE) system. Several techniques have been developed to generate the debug-oriented test patterns. We further show a silicon debug case of a 90nm design based on the proposed debug flow.
Improving Fault Isolation using Iterative Diagnosis
K. Gearhardt1, C. Schuermyer2, R. Guo2, (1)LSI Logic, Ft. Collins, CO, (2)Mentor Graphics, Wilsonville, OR
This paper presents an iterative diagnosis test generation framework to improve logic fault diagnosis resolution. Industrial examples are presented in this paper on how additional targeted pattern generation can be used to improve defect localization before physical failure analysis of a die. This enables failure analysis to be more effective by reducing the dependence on the more expensive physical fault isolation techniques.
Deterministic Fail Localization and Analysis of Scan Hold-Time Faults
J. Hwang1, J. Orbon2, D. Kim1, N. Seo1, E. Lee1, W. Choi1, Y. Jeong1, S. Cannon2, (1)Samsung Electronics, Giheung-gu Youngin-City, South Korea, (2)Verigy - Inovys DfX Solutions, Pleasanton, CA
This paper presents a deterministic diagnosis analysis method for hold-time faults in scan chains. The defects discussed in this paper are primarily seen at low Vdd values, so called Vdd-min defects; Vdd -max defects can also be a problem. Traditional approaches require data collection, the creation of additional patterns, and an iterative trip back to the tester. This is a time consuming process and does not always lead to a closed end solution. This paper presents a method to detect multiple hold-time faults in the chain using auto generated patterns and real-time on the tester. The data provides the locations of all of the hold-time faults for the selected failing voltage. The results are confirmed by the backside silicon probing technique, confirming the location of the fault.
Combining Refractive Solid Immersion Lens and Pulsed Laser Induced Techniques for Effective Defect Localization on Microprocessors
A. C. T. Quah1, S. H. Goh1, V. K. Ravikumar2, S. L. Phoa2, J. C. H. Phang1, V. Narang2, C. M. Chua3, J. M. Chin2, (1)National University of Singapore, Singapore, Singapore, (2)Advanced Micro Devices Singapore Pte Ltd, Singapore, Singapore, (3)SEMICAPS PTE LTD, Singapore, Singapore, Singapore
We have successfully applied both Refractive Solid Immersion Lens (RSIL) and pulsed-TIVA for defect localization and demonstrated significant improvements in defect localization precision. The full paper would include more case studies to demonstrate how RSIL and pulsing compliment each other to enhance both detection sensitivity and localization precision.
Evaluating PICA capability for future low voltage SOI chips
F. Stellari1, P. Song2, J. Vickers3, C. Shaw3, S. Kasapi4, R. Ispasoiu5, (1)IBM Research, Yorktown Heights, NY, (2)IBM, Yorktown Heights, NY, (3)DCG Systems, E. Fremont, CA, (4)NVIDIA, Santa Clara, CA, (5)Fairchild Imaging, Milpitas, CA
In this paper we evaluate the possibility of extending Picosecond Imaging Circuit Analysis (PICA) technology towards future low voltage SOI technologies. In particular, we investigate and quantify the gain offered by the InGaAs detector improvements devised by Credence Corp., now DCG Systems, the manufacturer of the Emiscope III PICA system used in this analysis. Experiments on a test chip fabricated in the IBM SOI 65 nm technology will demonstrate that the improved tool guarantees the same Signal-to-Noise Ratio (SNR) even at ~90 mV lower supply voltages. In the second part of the paper we also discuss various other acquisition optimizations of the system. Although the analysis presented here refers to a specific tool, the large majority of the results and discussions can easily be generalized and applied to other PICA systems and detectors, as well as low voltage bulk silicon technologies.
Applications of Nanoprober Technique to the characterization of mismatched behavior in advanced SRAM devices
H. S. Lin, C. M. Chen, UMC, Hsin-Chu City, Taiwan
The importance of understanding mismatched behavior in SRAM has increased as the technology node shrinks below 100nm. Using the nanoprober technique [1-3], MOS characteristics of failure bits in actual SRAM cells had been measured directly. After transistors that are failing had been identified, proper physical analyses actions were determined and taken to observe tiny defects. In this study, several types of nanoscopic defects such as offset spacer residue, salicide missing from active area, doping missing from the channel, gate oxide defects, contact barrier layer residue, and broken poly-gate silicide were successfully discovered.
Failure Analysis of Single Shared Column Fail in DRAM Using Nano Probing Technique
S. M. Kim, Hynix Semiconductor Inc., Icheon-si, Kyungki-do, South Korea
In this work, we have analyzed the single shared column fail on DRAM technology using nano probing system. If we have tried to analyze that failure only by the physical method, we couldn’t have found the correct fail mechanism. We could have sufficiently gathered the electrical information of fail transistor by nano probing system in advance, and then have revealed the mechanism of non-visible failure in some specific transistor.
Low Current AFP Characterization of Non-Visible Soft Transistor Defects
R. E. Mulder, Freescale Semiconductor, Austin, TX
The establishment of nano-probe technology as a failure analysis tool has given product analysts the ability to accesses all the nodes of any transistor on a chip allowing for the localization and complete electrical characterization of a defective transistor. This ability has resulted in a significant increase in number of individual soft transistors defects found as the cause of the device failure. These soft transistors defects are usually seen as Vt shifts, suppressed drive currents, or low level leakages. Usually, the cause of these soft defects is not identifiable by means of physical analysis such as the Scanning Election Microscope(SEM), Transmission Electron Microscope(TEM), or Atomic Force Microscopy(AFM)[1]. Therefore, other methods are being sought out to identify the root cause of transistor failures. Transistor modeling of possible defects using TCAD and comparing results to passing and failing transistor characterization is promising [2]; but accurate transistor modeling isn’t easy and is resource intensive. Another alternative is to figure out ways to identify more information out of the electrical characterization data that will indicate the possible root cause of the failure. This paper is a case study that starts the process of exploring alternative methods of electrical characterization and analysis of the data that will help identify the root cause failure mechanism for soft transistor failures.
Characterization and analysis of 45nm node SRAM standby leakage
D. Albert1, Z. Song1, S. Ippolito2, L. Fischer1, M. P. Tenney1, (1)IBM, Hopewell Junction, NY, (2)IBM, Yorktown Heights, NY
This paper describes a methodology to characterize and analyze SRAM cell standby current and identify the conduction paths and leakage mechanisms.
Investigation on Focused Ion Beam Induced Damage on Nanoscale SRAM by Nanoprobing
E. Hendarto, S. L. Toh, P. K. Tan, Y. W. Goh, J. L. Cai, Y. Z. Ma, Z. H. Mai, J. Lam, J. Sudijono, Chartered Semiconductor Manufacturing Pte. Ltd., Singapore, Singapore
FIB marks created to aid in failing site identification for nanoprobing have to be carried out with extreme caution. The Ga+ ions irradiated on the sample are sufficient to induce interface traps dominantly, shifting the electrical parameters drastically. For devices in the nanometer regime, charge neutralization with the use of a gate diode during FIB milling may no longer be feasible.
Oxidation of TiN ARC Layer as a Reliability Issue for ICs
M. J. McVeigh1, T. Bold2, W. J. Kindt3, A. Raz1, A. Gomes1, K. Y. Wong1, T. Inamine1, (1)National Semiconductor Corporation, Santa Clara, CA, (2)National Semiconductor Corporation, Arlington, TX, (3)National Semiconductor BV, Delft, Netherlands
During moisture-and-bias reliability stress tests of THBT (temperature and humidity biased test) and HAST (highly accelerated stress test) extensive electrochemical oxidation of a TiN ARC layer is seen to occur. This oxidation proceeds at the nominal temperatures and humidity levels associated with such THBT and HAST tests; excessive heating due to EOS (electrical overstress) was not involved. The oxidation rate increases with applied voltage. Oxidation requires the presence of adequate humidity to act as an electrolyte, and therefore is seen to propagate wherever moisture penetration can occur in the passivation dielectrics. The presence of a silicone gel die coating is found to render the die more susceptible to TiN oxidation. Electrical failures – typically open circuits or increased resistance due to corrosion – are found to occur as a consequence of this oxidation and its effect on the surrounding structures. This mechanism is a concern for integrated circuits with TiN in the upper metal layers, operating at voltages >5V in humid conditions. Two approaches at reducing this electrochemical reaction are offered.
Timing problems due to spacer bridging in a sub-100 nm product
H. V. J. Hassel, NXP Semiconductors, Nijmegen, Netherlands
Case study were combined effort of different expertises (design, modelling, FA)and advanced techniques RIL, AFM probing and TRE were necessary to solve a 90 nm yield issue caused by spacer bridging blocking the implant process.
A study of pad contamination defect and removal
K. A. Mohammad, L. J. Liu, S. F. Liew, S. F. Chong, D. G. Lee, S. F. Lee, B. C. Lee, X-FAB SARAWAK SDN. BHD., Kuching, Malaysia
The paper focus on pad contamination defect and removal technique. EDX and SEM employed to analyse the defect. Hit rate is 60% detected at outgoing inspection step. Fluorine based contamination source and contributor is discussed. Rework technique employed chemical solvent dipping time split and dry plasma etch. Successful criteria is passing e-test, e-sort and reliability test.
A study to remove heavy polymer remain on thick metal (> 3 micron) sidewall profile after metal etch solvent clean step
S. F. Liew, K. A. Mohammad, L. J. Liu, S. F. Chong, D. G. Lee, S. F. Lee, B. C. Lee, X-FAB SARAWAK SDN. BHD., Kuching, Malaysia
Removal of heavy polymer remain on thick metal sidewall profile.
Yield enhancement using a combination of wafer level Failure Analysis and defect isolation software: case studies
P. Simon1, M. Thétiot1, B. Picart1, C. Kardach2, H. Deslandes2, F. Dudkiewicz3, (1)ATMEL, ROUSSET, France, (2)DCG Systems, Fremont, CA, (3)Credence Systems Corporation, Milpitas, CA
This publication aims at showing how EMMI and OBIRCH analyses can be improved by software tools like a layout viewer with net tracing capability and CAD overlay. The methodology, introduced in the three case studies, proves that the major failure mode can be known quickly thanks to his defect mode and can be located accurately before the physical analysis.
A procedure for identifying the failure mechanism responsible for a pin-to-pin short in plastic mold compound integrated circuit packages
C. M. Nail1, J. J. Rocha2, L. Y. Wong2, (1)Independent, San Jose, CA, (2)National Semiconductor Corporation, Santa Clara, CA
A pin-to-pin short in an epoxy IC package could not be identified with conventional x-ray analysis. A combination of SQUID, parallel-grinding, OBIRCH and high-resolution low-power x-ray analysis techniques identified the short as copper leadframe residue.
Mis-identified Failures in FETs
M. Gores, Hi-Rel Labotories, Inc, Spokane, WA
Discussion on how FET failures that initially appear to be caused by overcurrent conditions are actually caused by open or intermittently open circuit gates.
Frontside and backside analysis of surface ESD
D. D. Daly, xilinx Ireland, Dublin, Ireland
Analysis of mechanical scrathces on die surface ,which turn out to be a surface ESD event. Some new details are discovered by doing backside FA using IR on Phemos and FIB with no CAD naviagtion to help.
Intermittent failures, challenges and strategies involved with finding root cause
N. Konkol, Intel Corporation, Hillsboro, OR
Intermittent failures are often difficult to find root cause. The reason is irregularity and inconsistency. When failures occur at irregular intervals or symptoms are inconsistent, it poses challenges to effectively discovering root cause. This abstract discusses different strategies that can be used to analyze motherboards that involved failure irregularity, symptom inconsistency or both.
Transient latch up analysis of power control device with combined light emission and backside transient interferometric mapping methods
M. Heer1, M. Street2, I. Smith2, F. Riedlberger2, D. Bonfert3, H. Gieser3, D. Pogany1, (1)Vienna University of Technology, Vienna, Austria, (2)Zetex Semiconductors plc, Oldham, United Kingdom, (3)Fraunhofer Institute IZM-M, Munich, Germany
We present a case study of a transient induced latch-up (TLU) problem, which was identified during the development of a 60V, 0.8um BiCMOS power control device. The mechanism was characterized by controlled transient latch-up testing and found to be fairly unusual, being triggered by a fast decreasing not necessarily negative spike or glitchon the positive supply pin. Emission Microscopy (EMMI) and Transient Interferometric Mapping (TIM) successfully located the parasitic SCR structure. TIM is an infra-red laser based technique for back side analysis. TIM analysis enables concurrent imaging of carrier injection and heating in nanosecond timescale providing more detailed information on the SCR action than more often used static photon emission or dynamic TLP / PICA imaging.
3D STEM tomography based failure analysis of 45 nm CMOS devices
F. Lorut1, D. Delille2, (1)STMicroelectronics, Crolles, France, (2)FEI Company, Eindhoven, Netherlands
Certain classes of device failures are difficult to analyse with the widely used FIB/SEM analysis techniques and do require complementary techniques to identify the root cause of the electrical failure. Regular TEM analysis of the defective zones is often inadequate because it is difficult to ensure that the defect is included in the (thin) TEM lamella and, if the TEM analysis is preceded by a FIB/SEM inspection, the defect risks to be (partially) destructed. Various case studies will be presented showing that 3D STEM tomography can provide conclusive analytical results, provided that special care is taken to prepare a well adapted sample.
Dopant Analysis on advanced CMOS technologies
F. Siegelin, A. Duebotzky, B. Danzfuss, S. Schoemann, Infineon Technologies, Munich, Germany
We will present the use of SIMS with high lateral resolution (nanoSIMS), chemical etching, TEM and SSRM for imaging implants in cross section an plan view direction.
SEM Si Doping Contrast Enhancement Using Sample Charging
Y. W. Hsieh, J. D. Russell, P. Y. Chen, Inotera Memories, Inc., Taoyuan, Taiwan
Using the surface insulator to enhanced dopant contrast.It differentiates SE (secondary electron) emission intensity from p-type and n-type doped regions to enhance dopant contrast. Dopant contrast is also influenced by imaging position and scanning time.
3-D image reconstruction in the scanning electron microscope
W. E. Vanderlinde, Laboratory for Physical Sciences, College Park, MD
In this paper, we demonstrate that commercial software running on a desktop computer can convert an SEM sterio-pair into a Digital Elevation Model (DEM) which is easy to view without any special equipment and can provide accurate measurements in all three dimensions.
High current focused ion beam instrument for destructive physical analysis applications
P. P. Tesch, N. S. Smith, N. P. Martin, D. Kinion, Oregon Physics LLC, Hillsboro, OR
A new FIB instrument has been developed with a volume removal rate that is more than 100X greater than existing FIBs based on a liquid metal ion source. This new FIB uses a RF plasma ion source on a commercially available FIB column to provide probe currents as high as 2 microAmperes. This new FIB has been operated with Oxygen, Argon, Xenon, or Helium providing metal free FIB milling.This high current FIB instrument is well suited to creating cross-sections for destructive physical analysis of structures from 100 micron to 1 mm in size. These types of cross-sections typically take a prohibitive amount of time with conventional FIB tools. This instrument also produces less structural damage than competing techniques for exposing large area cross-sections such as mechanical or chemical polishing.
Recent developments in TEM applications for the IC industry
L. Fu, F. Shen, Y. C. Wang, M. Strauss, A. Buxbaum, FEI, Hillsboro, OR
Three new developments in TEM including image aberration corrector, probe aberration corrector, and dual-axis STEM tomography will be studied in this paper.
Automated Serial-Section Polishing Tomography
J. A. Hunt, P. Prasad, E. Raz-Moyal, Gatan, Inc., Pleasanton, CA
A general implementation of automated serial-section polishing tomography is demonstrated and is expected to be applicable to a wide range of problems relevant to semiconductor backend processes and general materials science.
Applications of Scanning Near-field Photon Emission Microscopy
D. Isakov, National University of Singapore, Singapore, Singapore
A Scanning Near-field Photon Emission Microscope was applied for analysis of photon emission distribution from unipolar and bipolar silicon devices with resolution better than 50 nm for the wavelength range from 1000 nm to 1400 nm. A new probe was designed to achieve high spatial resolution, high sensitivity and high repeatability. Using the common knife-edge criterion, the spatial resolution of the images was estimated to be as small as 30 nm.
New Developments in High-Resolution X-Ray Computed Tomography for Non-Destructive Defect Detection in Next Generation Package Technologies
M. Pacheco, D. Goyal, Intel Corporation, Chandler, AZ
New Developments in High-Resolution X-Ray Computed Tomography for Non-Destructive Defect Detection in Next Generation Package Technologies. Mario Pacheco, Deepak Goyal Intel Corporation 5000 W. Chandler Blvd. Chandler, AZ, USA 85226 The assembly package development roadmap has been increasing interconnect complexity, component density, the number of stacked dice, material composition, while at the same time reducing critical dimensions. As a result of these trends, the isolation and root cause analysis of defects has become increasingly challenging for traditional analytical tools and techniques. In addition, reduced time-to-information and non-destructive approaches have become critical factors, introducing more challenges into the analytical tools development roadmap. One of these analytical capabilities is 2D x-ray imaging, which is also one of the more extensively used tools in the semiconductor industry to isolate and analyze defects in non-destructive fashion. Some of these capability challenges are the detection of metal migration and dendrite growth, C4 bump non-wetting and cracking, BGA solder fatigue and cracking, wirebonds shorting and die cracking in multi-stacked packages, etc. In this paper, we will demonstrate how next generation x-ray computed tomography (CT) technology [1] can be used to fulfill those analytical gaps. Results and Discussion. As first example of the several compelling case studies that we will present in full paper, we will discuss here a summary of non-destructive detection of non-wets in C4 solder joints. This application is key analytical gap for both root cause analysis and process development. Using 2D x-ray provides information regarding the shape of solder ball indicating non-wetting issues; however, when the shape is such that it is difficult to differentiate between passing and failing bumps due to 2D x-ray imaging limitations, this type of non-wet is known as “invisible”. Figure 1a shows the physical cross section pictures of both passing and non-wet failing solder bumps; this figure also shows that the best 2D x-ray image obtained using high-magnification at an oblique view angle cannot detect these types of non-wet solder bumps. In this case, using x-ray CT fully isolated the defective C4 bump, as can be seen in the virtual planar view of Figure 1a, or in the virtual cross section of Figure 1b. As second example of what we will report in the full paper, we will summarize the detection of cracks and partial cracks in C4 bumps in non-destructive fashion using x-ray CT, with sample sizes of up to 2 inches wide. In this application, destructive techniques like Dye and Pull produce artifacts and cannot be used in packages with underfill and physical cross-sectioning is a tedious and time consuming process. Figure 2 shows a comparison between virtual planar and cross sectional views for both a failing and passing C4 bumps; as can be seen, x-ray CT can provide a clear finger print of cracking issues, either using a virtual plane or a cross-sectional view. The slice surface of a good solder joint looks smooth and uniform; whereas the slice surface of a failing bump looks uneven. A similar situation occurs with the virtual cross-sectional views. One of the compelling capabilities of x-ray CT is the possibility of performing defect inspection during reliability testing to feedback to predictive reliability models, as well as at different steps during production for process development. We will demonstrate in the full paper how x-ray CT has been used to study cracking progression in C4 joints at different readout times in units under reliability testing. Other applications of the x-ray CT will be also included in the full paper, for instance wire bond shorting detection in low density interconnect packages (figure 3), and solder joint cracking detection in second level interconnect (figure 4), among others. The results and discussion in the full paper will demonstrate how the advancement in the x-ray CT technology can be used to fulfill key non-destructive fault isolation gaps in next generation package technologies. Key Words: x-ray, computed tomography, new package technology, fault isolation, failure analysis. [1] D. Scott, F. Duewer, S. Kamath, A. Lyon, D. Trapp, S. Wang, W. Yun, “A novel x-ray microtomography system with high resolution and throughput for non-destructive 3D imaging of advanced packages”, Proc. ISTFA, 2004, pp. 94-98
Flip-chip bump interface failure mechanisms in plastic BGA packages and failure analysis process flow
Z. Wang, International Rectifier, Temecula, CA
The present paper studies several failure mechanisms at both UBM and Cu substrate side for flip-chip die open contact failures in multiple-chip-module plastic BGA-LGA packages. A unique failure analysis process flow, starting from non-disturbance die level C-SAM, bump x-section followed by a two-stage bump interface integrity test including under-fill etching and bump pull test has been developed. Four different types of failure mechanism in multiple chip module that are associated with open/intermittent contact, ranging from device layout design, UBM forming process defect, to assembly related bump-substrate interface de-lamination have been identified. The established FA process has been proved to be efficient and accurate with repeatable result. It has facilitated and accelarated new product qualification processes for a line of high power MCM modules.
PCB Pad Cratering - Characterization Techniques and Challenges
S. Parupalli1, K. Newman2, M. Ahmad3, (1)Intel Corporation, Hillsboro, OR, (2)Sun Microsystems, santa clara, CA, (3)Cisco Systems, San Jose, CA
The transition to Pb-free materials has introduced many Printed Circuit Board (PCB) interconnect reliability challenges. New PCB laminate materials have been introduced to survive the higher Pb-free reflow temperatures. The increased stiffness of the most common Pb-free solder alloy, SnAgCu (SAC), relative to SnPb, coupled with reduced interconnect pitch and new laminate materials, have shifted the primary failure mode in mechanical bend and shock testing, from solder fractures to cratering underneath the PCB pads. Some standard characterization techniques (solder ball pull, solder ball shear, etc.) exist today for the assessment of solder ball mechanical fracture strength; however, it isn’t clear if these test methods would also provide characterization of PCB pad cratering susceptibility. This paper provides an overview of test methods being investigated by a PCB pad crater industry working group. This group was initiated during a break-out session in the 2006 Intel/IPC Pb-free symposium. The scope of this industry working group is two-fold: a) Standardization of PCB pad crater crack characterization and measurement methods b) Development of a quantitative quality metric for PCB pad cratering.
Stitch-bond-shearing in optoelectronic devices, caused by lead-free-wave-soldering - do we need improved wire-bonding methods?
P. Jacob1, M. Ruetsch2, (1)EMPA Swiss Federal Laboratories for Materials Testing and Research, Duebendorf, Switzerland, (2)Vossloh Kiepe GmbH, Duesseldorf, Germany
Lead-free soldering applies at higher temperatures, which becomes critcal for some optoelectronic devices due to their lower melting point of transparent mold. During soldering, external pins relax their mechanical tension of being plugged into breadboard-PCBs by slight movements, thus shearing stitchbonds or making them sensitive to vibration. To enhance reliability, the stitch bonding meeds to be improved
LEAD FREE SOLDER - GOLD METALLIZATION INTERDIFFUSION IN ELECTRONIC INTERCONNECTS - Challenges and their Control
N. ASRAR, SCHLUMBERGER, SUGAR LAND, TX
While most of the industries are striving very hard to produce totally lead-free electronic products, many concerns remain regarding lead-free solder joint reliability. One major concern is the robustness of gold metallization of the electronic components for lead-free soldering. Increasing gold content has been known to result in embrittlement and early failure in electronic assemblies. Therefore, information about the lead-free solder/gold metallization interdiffusion at high temperature applications is very important for controlling the technological processes for the reliability of the electronic interconnects. The challenges of solder/gold metallization interdiffusion during high temperature application/test are; gold embrittlement, intermetallics growth, void formation, and also tin-whisker formation. This paper illustrates few case histories of such challenges. After the thermal cycle test of one of the electronic circuit board, a lead-free solder joint fractured between the Oscillator and the pad. Both Oscillator and the pad on the printed circuit boards (PCB) were gold plated. Failure investigations using, microscopic examinations and material characterization by SEM/EDS, revealed numerous voids and high content of gold-tin intermetallic compound (IMC), AuSn4, in the Sn96 solder joints (Figures 1 and 2). These results confirmed that the synergistic effects of void formation, IMCs formation due to the thick gold plating, and coefficient of thermal expansion (CTE) mismatch between organic and ceramic substrates resulted in brittle fracture of the solder joint. Irregular shaped voids are most common in the solder joints of components with thick gold plating. As a result of higher gold dissolution, crystals of AuSn4 is formed, which increases the viscosity of the molten solder and degrades its spreadability. The increased viscosity also restricts the egress of gasses from solder during reflow, resulting in formation of numerous irregular shaped voids, which deteriorates the mechanical strength of the solder joints. Therefore, the plating thickness is the most influential characteristic of the gold deposit as it relates to the ultimate integrity of the solder connections in regards to gold embrittlement. The criticality of gold embrittlement is ensuring uniform dispersion of the gold in the melted solder and a final weight percent that depends on some other factors. The thinner Au deposits minimize Au-Sn intermetallic (AuSn4) formation and its concentration along the reaction interface. Importance of the thickness of the gold termination has been discussed and some parameters to optimizing the thickness of the gold termination have been suggested. In one of the printed circuit board Sn-Au intermetallic formation resulted in tin whisker formation (Figure 3). The circuit board was exposed to 120 h aging cycle at 180°C followed by 10 thermal cycles between - 40oC and 180oC before a failure was noticed. During inspection numerous white whiskers were observed over a lead-free solder surface. During a period of 140 hrs, 0.344 mm long whiskers were formed, which is the fastest growth rate of the whiskers formation reported so far. Scanning electron microscopy (SEM) and energy dispersive spectrometry (EDS) were used for microscopic examination and material characterization of the whiskers, end-cap metallization and the solder materials. The tin whisker formation was attributed to the compressive stress in the tin solder material, which was caused by diffusion of the end-cap metallization, formation of intermetallics, and thermal cycling of the soldered components (Figure 4). The findings contradict the speculation that high temperature annealing may reduce the risk of tin whisker formation. The findings also indicated that the application of conformal coating is not enough to contain the whisker growth within the coat, as has been claimed in the literature. Some remedial measures are suggested to control the lead-free solder-gold metallization diffusion in the electronics interconnects.
Investigation into failure modes of thick film power resistors
B. P. Sood1, M. Zagami2, A. Shrivastava3, A. Amin3, M. Azarian3, M. Pecht3, (1)CALCE, University of Maryland, College Park, MD, (2)Fairchild Controls Corp, Frederick, MD, (3)University of Maryland, College Park, MD
A detailed failure analysis methodology for thick film power resistors subjected to highly accelerated life testing (HALT) is presented in the paper.
Active Voltage Contrast and Seebeck Effect Imaging as Complementary Techniques for Localization of Resistive Interconnections
I. Österreicher, U. Rossberg, S. Eckl, Infineon Technologies Dresden GmbH & Co. OHG, Dresden, Germany
The paper focuses on how Active Voltag Contrast and Seebeck Effect Imaging yield different information and how they complement each other when applied to high resistive chains of interconnections. Only the combination of AVC and SEI delivers the complete view on resistive interconnection issues and covers the full resistance range. Active Voltage Contrast allows localization of resistive interconnections under conditions that have previously prevented successful analysis, especially contacts on substrate or chains with slightly increased resistance. Seebeck Effect Imaging provides additional lateral resistance mapping in case of soft opens and makes differences between the interconnections visible with very high sensitivity.
A Logical Problem Solving Process for High Via Resistance Root Cause Analysis
K. Li, P. Liu, J. Teong, Chartered Semiconductor Manufacturing Ltd, Singapore, Singapore
This paper presents a step-by-step logic thinking process for a field return high via reistance issue. It involves electrical fault isolation, process commonality check, physical characterization, design of experiment and logic thinking. It is found that the non-optimized via cleaning recipe (due to the introduction of CO2 into DI water) causes damage to the Al at the via bottom, and the single via on big metal structure has rigorous stress condition. Therefore this structure is more vulnerable to Al intrusion and high via resistance. A redesign of the structure, such as adding one more via onto the big metal piece, will alleviate the rigorous stress condition and reduce the failure rate.
Vdd Leakage Analysis by a Combination of Various Failure Analysis Techniques
Z. Song, S. B. Ippolito, P. J. McGinnis, A. Shore, B. Paulucci, T. Kane, M. P. Tenney, F. G. Trudeau, A. W. Kozaczka, IBM, Hopewell Junction, NY
Vdd leakage issues can be addressed by global fault isolation with LCA, photoemission or laser stimulation techniques. However, the hot spot detected by these techniques may be a secondary effect. To pinpoint the exact defective location, further local fault isolation may be required by electrical probing. Once the defective location is identified, the appropriate follow-on physical failure analysis technique can be chosen for the root cause analysis. This paper will describe a thorough analysis process for Vdd leakage failure by a combination of various failure analysis techniques.
Physical Failure Analysis Techniques and Studies on Vertical Short Issue of 65nm Devices
P. K. Tan, Z. H. Mai, S. L. Toh, E. Hendarto, Q. Deng, Y. W. Goh, J. L. Cai, Y. Z. Ma, H. B. Lin, L. Zhu, J. Yu, H. L. Li, Q. F. Wang, H. Tan, R. He, J. Lam, Chartered Semiconductor Manufacturing Pte. Ltd., Singapore, Singapore
With the scaling down of semiconductor devices to nanometer range, physical failure analysis (PFA) has become more challenging. In this paper, a different method of performing PFA to identify a physical vertical short of inter-metal layer in nanoscale devices is discussed.
Fast root cause analysis based on electrical defect localization
M. B. Schmidt1, L. A. Dworkin1, C. Hess2, M. Squcciarini2, S. Yu2, J. Burrows2, (1)FEI Company, Hillsboro, OR, (2)PDF Solutions Inc., San Jose, CA
This paper discusses a new technique for localizing and determining the root cause of yield limiting defects detected after electrical test. The technique highlights the union between electrical test structure layout and FIB/SEM Dualbeam.
Failure Analysis for Gate Oxide Breakdown
X. F. F. Chen, M. Li, Q. Guo, K. Chien, Y. Gao, Semicoductor Manufacturing International Co., Shanghai, China
Two VBD failure cases were studied in this work. To overcome the EFA and PFA limitation, comparison analysis was applied to identify the root cause of VBD failure. In addition, new lapping down method was used to access the capacitance.
Non invasive Failure Analysis of Passive Electronic Devices in Wireless Modules using X-ray microtomography (MicroCT)
T. Pendleton1, L. Hunter2, S. Lau2, (1)RFMD, Greensboro, NC, (2)Xradia, Inc., Concord, CA
We report an non invasive failure analysis (FA) technique, in 3D of passive devices in wireless modules using a MicroCT (x-ray microtomography system). While the price of passive devices may not be significant, they are integrated into more expensive modules and circuits in wireless devices, which impacts reliability. Major FA problems in these passive devices include solder reflow, open solder connections and/or interconnect related defects, which cannot be easily detected with conventional techniques, such as 2D X-ray analysis, can now be characterized non invasive in 3D and 2D CT slices.
Scanning Acoustic Microscopy for Solder Joint Failure Analysis and Design Improvements
R. Varma, J. Bartolovich, V. Brzozowski, Northrop Grumman Corporation, Baltimore, MD
This paper reports using Scanning Acoustic Microscopy for solder joint failure analysis and process and design improvements. There are reliability concerns associated with solder voids or non-wetting of the solder to the bond pads which is particularly important for higher electrical power or temperature applications. Defects in solder can also occur and grow during operation and thermal cycling. Sonoscan is an attractive non-destructive test to characterize solder joints and is often used to study the growth of defects during life test simulations. X-ray imaging cannot identify very small defects, particularly non-wetting and delamination because of poor resolution. The instrument used in this study was a C-SAM (C-Mode Scanning Acoustic Microscopy) operating in reflection mode at 30-100 MHz. We have identified voids inherent in the solder layer as well as delamination at the package to solder and solder to the heat-sink interfaces. C-SAM results confirmed that the delamination was caused by CTE mismatch of the materials as well as the mechanical stresses caused by higher level package integration and module assemblies. Thermal cycling studies have shown that typically the voids do not grow whereas delamination does. These results were used to improve product reliability by minimizing defects in solder joint by changes in process and mechanical designs.
Application of Lock-In-Thermography for three-dimensional localisation of electrical defects inside of complex packaged devices
C. Schmidt, F. Altmann, C. Grosse, F. Naumann, Fraunhofer Institute for Mechanics of Materials, Halle, Germany
Lock-in-Thermography (LIT) is a new approach for non destructive defect localisation inside packaged devices. This paper will present further improvements of the LIT method locating electrical defects like shorts and resistive opens inside of complex three dimensional devices. Different test samples with defined heat sources and additional thermal simulation were used to investigate heat transfer through a packaged device and optimize LIT parameters. For three dimensional hot spot localisation the phase shift between the stimulation of the defect and the correspondet thermal signal at the device surface were investigated.
An analytical technique to assess the risk of laser damage to encapsulated Integrated circuits during package laser marking
J. M. Patterson, Applied Micro Circuits Corp, san diego, CA
A new cause for failure of integrated circuits was reported in a paper by Intel at the 2007 ISTFA conference wherein damage to the encapsulated integrated circuit was induced during laser package marking due to local heating. A path is provided through the epoxy mold compound to the die surface by the spheres of glass filler for thin packages. This paper discusses a method to examine packages that may be susceptible to this failure mechanism. The method uses Optical Beam Induced Current (OBIC) and Thermally Induced Voltage Alteration (TIVA) laser imaging techniques to electrically detect the optical transmission of thin packages. The enclosed integrated circuit is the detector and the laser is scanned on the outside of the package. Example: A good sample (passing ATE) was examined using the OBIC imaging technique on a completed device. This imaging was performed through the top of the package with the mold compound intact. Electrical connection is made to two power supply pins of the device and those connections go to a current amplifier for video imaging as the OBIC laser is scanned. The OBIC laser is 1065 nanometers wavelength and does not ablate the epoxy mold compound. But the glass spheres in the epoxy will pass that wavelength. Also, this wavelength will generate electron hole pairs in the semiconductor die and create a current if the laser light reaches the die surface (and the junctions are not covered by metal). When the first sample was examined this way, at least eleven sites were detected where the laser reached the die through a path of glass spheres in the mold compound covering the die. The package marking laser is more powerful than the OBIC laser. It ablates the mold compound and can cause damage to the die. Reference picture in figure 1 below. Figure 1: OBIC image through the top of the package over the die area. The white spots are the glass spheres in the epoxy mold compound in the reflected mode. The green spots are locations where the OBIC laser reached the die surface and caused a current in the semiconductor junctions through a path of glass spheres. About eleven sites are detected indicating a path to the I.C. Figure 2: TIVA image of the same device type as in figure 1 using a 1340 nanometer wavelength laser. The top of the package was polished to a depth that just removed the laser marking. The red and green spots are locations where the laser goes through glass filler particles that are lined up to the die surface and is detected electrically by the circuit. The white spots are the glass filler particles on the surface showing up in the reflected image.
Techniques for identification of silver migration in plastic encapsulated devices assembled with molding compound containing red phosphorus flame retardant material
R. Hylton, Maxim Integrated Products, Hillsboro, OR
This paper describes the electrical signatures and the failure analysis techniques used to identify plastic encapsulated devices that have failed because of adjacent pin leakages as a result of silver migration. This migration has been associated with molding compounds that utilize red phosphorous as the flame retardant material.
Emerging Techniques for the Characterization of Nano-Mechanical Properties of Integrated Circuit Components
R. Premachandran Nair, N. Randall, CSM Instruments, Needham, MA
Manufacturing In-Line Whole Wafer Focused Ion Beam (FIB) Memory Address Descramble Verification
S. B. Herschbein, C. H. H. Kang, S. L. Jansen, A. S. Dalton, IBM Systems & Technology, Hopewell Junction, NY
The installation of a full wafer Dual Beam FIB on the wafer fabrication line has created the opportunity to move certain traditional failure analysis tasks out of the lab and onto the factory floor. Over the past few years numerous papers have been published on the value of the in-line FIB as an early learning tool for construction analysis and defect root-cause determination. With appropriate precautions, however, we believe substantial value can also be derived by leveraging this tool for selective circuit editing on partially processed wafers. Engineering lots that have completed the basic transistor fabrication process can be routed to the FIB for mid or back end wiring changes, then returned to the line to complete the wafer build. While we have successfully performed full logic changes in-line (cuts and conductor deposition to correct errors), this paper will discuss our extensive experience in doing simple 'deletes' to simulate memory array defects. In this procedure we ‘write’ a pattern of defects directly into a memory array at an early mask level. Electrical bit mapping of these sites upon wafer completion is then used to verify correlation between logical and physical addressing of the array. This early feedback in-line methodology has worked so well that it has almost entirely displaced the complex laboratory procedure of backside FIB memory array descramble verification.
An Analysis of Tungsten FIB-made Via Resistance
D. W. Niles1, J. Meyer1, R. W. Kee1, M. DiBattista2, (1)Avago Technologies, Fort Collins, CO, (2)FEI Corporation, Hillsboro, OR
Avago and FEI have collaborated to study and measure the resistances of multiple W vias deposited by a FIB, using a unique wafer thin-film structure. We will present the measured resistances compared to a classical model.
Backside Circuit Edit on Full-Thickness Silicon Devices
C. Rue1, K. Skinner1, R. Hoelle1, S. B. Herschbein2, C. Scrudato2, (1)FEI Company, Hillsboro, OR, (2)IBM Systems & Technology, Hopewell Junction, NY
The feasibility of performing backside circuit edit on unthinned die is examined, with special attention to IR imaging, silicon trenching, and high-accuracy navigation within the trench.
Insulator Deposition for Through Conductor Editing
C. Richardson1, T. Malik2, V. Makarov2, (1)Abound Solar, Fort Collins, CO, (2)DCG Systems Inc., Fremont, CA
The deposition of FIB deposited insulator (I-dep) for circuit edit was investigated about ten years ago [1, 2, 3,4,5,6,] and therefore when there was more space available for an edit. In circuit edit I-dep has several applications: A. Repassivation of an edit site after an edit B. Isolation of 2 newly formed traces C. Sealing a copper cut as copper is prone to corrosion D. Protecting the bottom of a trench when backside editing (also makes an anti-reflective coating, ARC) E. Lining an access hole through a power plane or through Si when backside editing (See Fig. 1). Application E should be considered the most critical of these several applications. Bringing a signal through a conductive material such as the power plane or Si, requires that the access hole be lined with insulator. With the onset of low-k technologies, the increase in backside bulk design repair applications, and increase in SOI applications, the more critical the role insulator deposition will play.
Creation of Solid Immersion Lenses in Bulk Silicon Using Focused Ion Beam Backside Editing Techniques
P. Scholz, Berlin University of Technology, Berlin, Germany
S/D LDD Junction Stain/Delineation by Electrochemical Displacement with Illumination
R. L. Chiu, T. Chen, S. Chen, WaferTech LLC, Camas, WA
This article describes the use of an optimized electrochemical displacement technique with illumination to clearly delineate the p-n junction on Si in short channel devices. In this process, the samples are exposed to a light source while in an aqueous CuSO4/HF/H2SO4 solution which induces a junction voltage between n- and p- type silicon. The n+/p+ dopant regions become the anode/cathode electrode plates. The treatment is simple and reproducible which makes it a practical method for identifying junction related problems at localized areas on a chip. An example is provided to show the effectiveness of this technique in identifying the root cause of an N+ shift issue that had caused significant yield loss on a 0.18u mix-mode device.
A New Method of Wafer Level Plan View TEM Sample Preparation by DualBeam
C. H. H. Kang1, M. Gribelyuk1, C. Senowitz2, (1)IBM Systems & Technology, Hopewell Junction, NY, (2)FEI Company, Hillsboro, OR
There is a high level of interest on the 300mm wafer processing line in obtaining defect analysis with fast turn around time, while preserving wafers. As the size of killer defects continues to shrink, conventional in-line characterization methods are failing to provide answers required by the semiconductor industry. Transmission electron microscopy is becoming more important than ever for obtaining high resolution images and high materials contrast. Cross-sectional style TEM sample preparation techniques by DualBeam FIB systems have been introduced, and are widely used in both laboratory and manufacturing lines with either in-situ or ex-situ plucking methods. By contrast, however, the plan view TEM sample has only been prepared in the laboratory environmental, and only after breaking the wafer. In this paper we introduce for the first time a new methodology for in-line plan view TEM sample preparation at the 300mm wafer level that does not require breaking the wafer. This novel TEM sample preparation technique allows investigation of in-plan defects that are not otherwise easily imaged.
Embedded Gold Markers for Improved TEM/STEM Tomography Reconstruction
J. S. Luo, C. C. Huang, J. D. Russell, Inotera Memories, Inc., Taoyuan, Taiwan
We have shown that our novel electron tomography sample preparation method is a useful technique to improve the critical image alignment procedure, which is essential for successful tomography. We have also successfully applied a modified version of the technique to deposit gold beads onto TEM pillar samples for much improved 3-D reconstruction.
Timing Sensitivity Analysis of Logical Nodes in Scan Design Integrated Circuits by Pulsed Diode Laser Stimulation
T. Kiyan1, C. Brillert2, C. Boit1, (1)Berlin University of Technology, Berlin, Germany, (2)Infineon Technologies AG, Munich, Germany
Since scan design is a widely used methodology to improve the testability of the devices, the timing analysis of the scan chain structures is necessary to characterize the performance of a clock driven circuit. In this paper, a methodology will be presented based upon laser stimulation which localises the fault relevant sites in a scan chain cell and a comparison of continuous wave and pulsed laser operation. The pulse of the laser is externally triggered and can easily be shifted to various time slots in reference to clock and scan pattern. It is demonstrated that the technique is able to identify the most sensitive signal condition for fault injection with a better time resolution than pulse width of the laser, a significant improvement for failure analysis of Integrated Circuits.
Dual Port RAM MBIST Failure Analysis using Time Resolved Dynamic Laser Stimulation
J. A. Shaw1, C. H. McMahon1, F. Beaudoin2, (1)LSI Corporation, Fort Collins, CO, (2)IBM
A Dual Port SRAM Memory Built-in Self Test (MBIST) failure within an embedded Dual Port memory array was analyzed using Dynamic Laser Stimulation (DLS). This technique rapidly localized the failing area within the memory circuits. However from the MBIST results and the DLS localization signature it was not possible to identify with certainty if the failure was related to a write or read operation. In order to target specific sequences of the MBIST pattern during DLS, the laser output was modulated synchronously with the test pattern. To achieve this laser modulation an Electro-Optic Modulator (EOM) was used. Such a scheme allowed to stimulate only specific write or read operations of the MBIST pattern. The end result is a set of Time Resolved Dynamic Laser Stimulation (TR-DLS) maps obtained for each operation of the MBIST pattern. Those clearly identified that the read operation was failing and that the sense amp was the cause. The TR-DLS technique also provided different DLS signature between a Port AB read and a Port B read sequence.
Mixed Frequency Detection of Thermal Laser Stimulation (TLS) and its Application in Failure Analysis
Z. Qian, C. Brillert, C. Burmer, Infineon Technologies AG, Munich, Germany
This abstract has introduced a new localization method called Mixed Frequency Thermal Laser Stimulation (MFTLS). At one side, this method will increase the dynamic TLS sensitivity by shifting the lockin detection frequency to a lower optimized value. On the other hand, this method can also be applied to the direct localization of the open site in metal line and cross talk. For open metal lines, the experiment results correlates well with the capacitor model for the gap in the open metal line. In order to obtain a better open detection, the frequency f2 must be raised to an optimized value. In the full paper, more details about this technique and MFTLS applications in FA will be showed in some case studies in the 90nm and 65nm techniques.
Differentiation between artifacts and true defects in 45 nm BEOL structures in MTLS technique
A. Reverdy1, P. Perdu2, M. De La Bardonnie3, H. Murray4, P. Poirier5, B. Domengès6, (1)NXP Semiconductors, Caen, France, (2)CNES - French Space Agency, Toulouse, France, (3)NXP Semiconductors, Crolles, France, (4)LaMIP, Caen, France, (5)NXP Semiconductors, CAEN, France, (6)CNRT-CNRS, Caen, France
Modulated Thermal Laser Stimulation (MTLS) has been established as a key technique to accurately localize defects at elementary structure level in deep submicron technologies. It has been achieved by Thermal Time Constant analysis (TTC) which allows knowing the dynamics of thermal exchanges. In this paper, we demonstrate for the first time the efficiency of this technique on 45 nm Back End Of the Line (BEOL) test structure in image mode and we underline the efficiency of the developed technique to differentiate artifacts and true defects in 45 nm BEOL structures.
Nano CV Probe Characterization Analysis Comparison with Conventional CV Probe Pad Analysis
T. Kane1, M. P. Tenney1, A. N. Erickson2, P. Harris2, (1)IBM, Hopewell Junction, NY, (2)Multiprobe, Inc, Santa Barbara, CA
The introduction of nano CV characterization of discrete MOSFET devices and the method of performing scanning capacitance imaging has been previously presented. By nano probing at CA contact level discrete MOSFET devices that are routinely analyzed at probe pad level with conventional CV measurements, a means of comparison can be established to compare the results obtained by both methods.
Analysis of Deep Trench Node Leakage Depth by applying Current Imaging Technique at Silicon Level
S. Doering, M. Seitz, P. Rodger, W. Werner, Qimonda Dresden GmbH & Co. OHG, Dresden, Germany
It was shown that using AFM based probing equipment additional information regarding the location of the node leakage could be obtained. Since the deep trench is a vertical device, the gained z-information is of value. In this example study three analysis steps were done. At first the node leakage was verified at contact level. In a second step the sample was deprocessed into the pWell level and a current image was obtained, confirming the node leakage to be located below this level. In the third step the sample was further deprocessed to the edge of the nWell level. Again a current image was obtained, this time showing no leakage any more. With those three measurements we confined the node leakage to the small (compared to the whole deep trench) nWell region.
Backside failure analysis by electroluminescence on microwave devices
M. Bouya1, D. CARISETTI1, P. DELAQUEZE1, J. C. Clement1, P. Perdu2, (1)Thales Research and Technology, Palaiseau, France, (2)CNES - French Space Agency, Toulouse, France
HBT (Heterojunction bipolar transistor) and HEMT (High Electron Mobility Transistor) III-V transistors are paying a key role for power and RF low noise applications but their failure analysis are very challenging: Active area thickness is only few nanometers, backside failure localization is mandatory because of thermal drain or metal bridge covering the front side, materials involved are a mixture of ultimate hardness and high chemical sensitivity while failure mechanisms strongly differ from Si technologies. To face these challenges, we have developed a complete approach, without degrading the component, based on Backside failure analysis by electroluminescence. Its efficiency and completeness has been demonstrated through case studies that will be discussed in detail in the final paper.
Photon Emission Spectral Signatures of AlGaN/GaN HEMT for Functional and Reliability Analysis
A. M. Glowacki1, C. Boit1, R. Lossy2, J. Würfl2, (1)TUB Berlin University of Technology, Berlin, Germany, (2)Ferdinand Braun Institut für Höchstfrequenztechnik, Berlin, Germany
Non-degraded and degraded AlGaN/GaN HEMT devices have been characterized electrically and investigated in various operating modes using integral and spectrally resolved photon emission (PE). In non-degraded device the PE dependence on the gate voltage is similar to that known from silicon MOSFETs, although the physical origin is different. The maximum exists at the intermediate gate voltage of (around -3.6V). For the positions of the strongest degradation in degraded devices this shape is disturbed. Two or more maxima could be measured. PE spectroscopy was performed at various bias conditions. For both devices broad spectra have been obtained in a wavelength regime from visible to near-infrared, including local performance variations. Signatures of the degradation have been determined in the electrical characterization, in integral PE and in the PE spectrum.
Laser Scanning Localization Technique for Fast Analysis of High Speed DRAM devices
M. Versen1, A. Schramm2, J. Schnepp2, S. Hoch2, T. Vikas2, D. Diaconescu3, (1)University of Applied Sciences Rosenheim, Rosenheim, Germany, (2)Qimonda AG, Neubiberg, Germany, (3)Infineon Technologies AG, Munich, Germany
Soft defect localization (SDL) is a method of laser scanning microscopy that utilizes the changing pass/fail behavior of an integrated circuit under test and temperature influence. Historically the pass and fail states are evaluated by a tester that leads to long and impracticable measurement times for dynamic random access memories (DRAM). The new method using a high speed comparison device allows SDL image acquisition times of a few minutes and a localization of functional DRAM fails that are caused by defects in the DRAM periphery that has not been possible before. This new method speeds up significantly the turn-around time in the failure analysis (FA) process compared to knowledge based FA.
Novel application of the OBIRCh amplifier for timing failure localization
M. A. Sienkiewicz1, S. Brule2, A. Firiti3, O. Crepel2, (1)CNES (French Space Agency) (& Freescale Semiconductor), Toulouse, France, (2)Freescale Semiconductor SAS, Toulouse, France, (3)Freescale Semiconductor, Toulouse, France
Soft Defect localization laser techniques in dynamically working semiconductor devices are widely used for Failure Analysis (FA). In this context, many AC signal-oriented analysis methods have been introduced to date (SDL, LADA…) or are under development (xVM…). Sophisticated tools are available to localize these kind of failures but they are expensive and not every FA laboratory can afford them. By fully exploiting the capabilities of static localization tools it is possible to deal with timing issues. In this abstract, we propose a novel application of the OBIRCh amplifier related to the timing issues on a real case study (Mixed-Mode device). This novel and very simple application makes the analysis flow time-attractive and enlarges the application field of mapping techniques on the existing tools.
Analog Building Blocks: Circuits and Devices
J. Fullerton1, D. Sargent2, S. Haidar2, J. McCarthy2, R. Fecteau2, (1)Analog Devices Inc., Wilmington, MA, (2)Analog Devices Inc., Cambridge, MA
Diagnosing Analog Circuits
S. Ipek1, M. Salinas1, A. Evangelista1, S. Swieck1, R. Fecteau2, J. Fullerton Jr.1, (1)Analog Devices, Wilmington, MA, (2)Analog Devices Inc., Cambridge, MA
CMOS Electronics and Defect Analysis
C. Hawkins, University of New Mexico, Albuquerque, NM
Flash Memory Failure Analysis
M. Shuller, Intel Corporation, Chandler, AZ
Failure Analysis of SRAM Memory
S. Gunturi, Texas Instruments, Inc., Dallas, TX
Emerging Trends in Failure Modes of Nanotechnology
T. Kane, IBM, Hopewell Junction, NY
ESD Testing of Electronic Components using the Transmission Line Pulse Methodology
L. G. Henry, ESD-TLP Consulting & Testing, Fremont,, CA
Surface ESD (ESDFOS) in Assembly Fab Machineries as a Functional and Reliability Risk - Failure Analysis, Tool Diagnosis and On-Site-Remedies
P. Jacob, EMPA Swiss Federal Laboratories for Materials Testing and Research, Duebendorf, Switzerland
Failure Analysis Flow Decision Tree
C. Richardson1, K. S. Wills2, (1)Abound Solar, Fort Collins, CO, (2)Independent Consultant, Sugar Land, TX
Classic Case Histories
J. Colvin, FA Instruments, San Jose, CA
Delayering Techniques: Dry Processes, Wet Chemical, Parallel Lapping
K. S. Wills1, S. Perungulam2, (1)Independent Consultant, Sugar Land, TX, (2)Texas Instruments, Stafford,, TX
Case Studies of Localized Degradation Phenomena in Copper Interconnects during Electromigration Testing
M. A. Meyer1, E. Langer2, H. J. Engelmann1, E. Zschech1, (1)AMD Saxony LLC & Co. KG, Dresden, Germany, (2)GLOBALFOUNDRIES, Dresden, Germany
The Role of the AFM in Yield and Failure Analysis
J. Colvin, FA Instruments, San Jose, CA
Flip-Chip and Backside Analysis Techniques
E. I. Cole1, D. L. Barton2, K. Bernhard-Höfer3, (1)Sandia National laboratories, Albuquerque, NM, (2)Sandia National Laboratories, Albuquerque, NM, (3)Infineon, Munich, Germany
Lock-in Thermography
O. Breitenstein, Max Planck Institute of Microstructure Physics, Halle, Germany
The Pivotal Role of AFP Nanoscale Failure Analysis
R. E. Mulder, Silicon Labs, Austin, TX
Beam-Based Defect Localization Techniques
E. I. Cole, Sandia National laboratories, Albuquerque, NM
Photonic Localization Techniques
C. Boit, TUB Berlin University of Technology, Berlin, Germany
Fundamentals of Laser Based FA Techniques
R. A. Falk, Quantum Focus Instruments, Tukwila, WA
Failure Localization with Active and Passive Voltage Contrast in FIB and SEM
R. Rosenkranz, Qimonda Dresden GmbH & Co. OHG, Dresden, Germany
Focused Ion Beam — a Sample Preparation Tool
K. Hooghan, Hooghan Consultancy and Services, Murphy, TX
FIB – A Design Repair / Fault Isolation Tool
S. Herschbein1, C. Richardson2, C. Rue3, (1)IBM Systems & Technology, Hopewell Junction, NY, (2)Abound Solar, Fort Collins, CO, (3)FEI Company, Hillsboro, OR
Cost of FA and Debug
S. P. Maher, Oklahoma Christian University, Oklahoma City, OK
Failure Analysis Lab Management Overview
R. Ross, Independent, VT
Materials Characterization - Surface Analysis of Assembly Materials
A. Proctor, D. B. Pathangey, Intel Corporation, Chandler, AZ
Materials Analysis as a Support Function
T. A. Anderson, ON Semiconductor, Phoenix, AZ
Introduction to Microelectromechanical Systems (MEMS) Materials and Fabrication Processes
J. A. Walraven, Sandia National Labs, Albuquerque, NM
Optoelectronic Techniques for MEMS and Electronic Packaging Characterization
C. Furlong, Worcester Polytechnic Institute, WPI, Worcester, MA
Optical and Infrared FA Microscopy
J. J. McDonald, Quantum Focus Instruments Corporation, Vista, CA
TEM Techniques for FA
S. Subramanian, Freescale Semiconductor, Inc., Austin, TX
Advanced Techniques in Sample Preparation and TEM Analysis of Microelectronic Materials
R. R. Cerchiara, E.A. Fischione Instruments, Inc., Export, PA
SEM: From Basics to Ultra-High Resolution
W. E. Vanderlinde, Laboratory for Physical Sciences, College Park, MD
Chip Scale Package and Its Failure Analysis Challenges
S. Li, Spansion Inc, Sunnyvale, CA
Lead Free Challenges
V. S. Vasudevan, Intel Corporation, Hillsboro, OR
X-Ray & SAM Challenges for IC Package Inspection
T. Moore, Omniprobe, Inc., Dallas, TX
Time Domain Reflectometry
D. Smolyansky, Tektronix, Inc., Beaverton, OR
Magnetic Based Current Imaging for Fault Isolation in Die and Packages
L. A. Knauss, Booz Allen Hamilton, Annapolis Junction, MD
Repackaging
R. Harrison, D. Maxwell, Texas Instruments, Dallas, TX
Enhanced De-Packaging and Chip Access FA Techniques
O. Diaz de Leon, Texas Instruments, Stafford, TX
Logic Diagnostics: Techniques, Applications and Challenges
S. Venkataraman, Intel Corporation, Hillsboro, OR
From Scan Testing to Embedded Testing
M. Keim, Mentor Graphics, Wilsonville, OR
Defect-Oriented Testing
R. Aitken, Artisan Components, Sunnyvale, CA
Yield Basics for Failure Analysis including 300mm wafer and Cu technology
T. Myers1, D. Albert2, (1)ON Semiconductor, Gresham, OR, (2)IBM, Hopewell Junction, NY
FA Case Histories using ATPG and SCAN Diagnostics:
K. S. Wills, Independent Consultant, Sugar Land, TX