C. Burmer, Infineon Technologies AG, Munich, Germany; R. Guo, W. T. Cheng, X. Lin, Mentor Graphics, Wilsonville, OR; B. Benware, Mentor Graphics, OR

Summary: We describe a silicon debug flow that uses debug-oriented scan test patterns to improve the efficiency of physical fault isolation. The debug-oriented test patterns are especially generated to meet the requirement of fault isolation using time-resolved emission (TRE) system. Several techniques have been developed to generate the debug-oriented test patterns. We further show a silicon debug case of a 90nm design based on the proposed debug flow.