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Wednesday, November 5, 2008 - 8:00 AM

S/D LDD Junction Stain/Delineation by Electrochemical Displacement with Illumination

R. L. Chiu, T. Chen, S. Chen, WaferTech LLC, Camas, WA

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Summary: This article describes the use of an optimized electrochemical displacement technique with illumination to clearly delineate the p-n junction on Si in short channel devices. In this process, the samples are exposed to a light source while in an aqueous CuSO4/HF/H2SO4 solution which induces a junction voltage between n- and p- type silicon. The n+/p+ dopant regions become the anode/cathode electrode plates. The treatment is simple and reproducible which makes it a practical method for identifying junction related problems at localized areas on a chip. An example is provided to show the effectiveness of this technique in identifying the root cause of an N+ shift issue that had caused significant yield loss on a 0.18u mix-mode device.