K. Gearhardt, LSI Logic, Ft. Collins, CO; C. Schuermyer, R. Guo, Mentor Graphics, Wilsonville, OR

Summary: This paper presents an iterative diagnosis test generation framework to improve logic fault diagnosis resolution. Industrial examples are presented in this paper on how additional targeted pattern generation can be used to improve defect localization before physical failure analysis of a die. This enables failure analysis to be more effective by reducing the dependence on the more expensive physical fault isolation techniques.