J. Hwang, D. Kim, N. Seo, E. Lee, W. Choi, Y. Jeong, Samsung Electronics, Giheung-gu Youngin-City, South Korea; J. Orbon, S. Cannon, Verigy - Inovys DfX Solutions, Pleasanton, CA

Summary: This paper presents a deterministic diagnosis analysis method for hold-time faults in scan chains. The defects discussed in this paper are primarily seen at low Vdd values, so called Vdd-min defects; Vdd -max defects can also be a problem. Traditional approaches require data collection, the creation of additional patterns, and an iterative trip back to the tester. This is a time consuming process and does not always lead to a closed end solution. This paper presents a method to detect multiple hold-time faults in the chain using auto generated patterns and real-time on the tester. The data provides the locations of all of the hold-time faults for the selected failing voltage. The results are confirmed by the backside silicon probing technique, confirming the location of the fault.