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Wednesday, November 5, 2008 - 5:10 PM

Evaluating PICA capability for future low voltage SOI chips

F. Stellari, IBM Research, Yorktown Heights, NY; P. Song, IBM, Yorktown Heights, NY; J. Vickers, C. Shaw, DCG Systems, E. Fremont, CA; S. Kasapi, NVIDIA, Santa Clara, CA; R. Ispasoiu, Fairchild Imaging, Milpitas, CA

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Summary: In this paper we evaluate the possibility of extending Picosecond Imaging Circuit Analysis (PICA) technology towards future low voltage SOI technologies. In particular, we investigate and quantify the gain offered by the InGaAs detector improvements devised by Credence Corp., now DCG Systems, the manufacturer of the Emiscope III PICA system used in this analysis. Experiments on a test chip fabricated in the IBM SOI 65 nm technology will demonstrate that the improved tool guarantees the same Signal-to-Noise Ratio (SNR) even at ~90 mV lower supply voltages. In the second part of the paper we also discuss various other acquisition optimizations of the system. Although the analysis presented here refers to a specific tool, the large majority of the results and discussions can easily be generalized and applied to other PICA systems and detectors, as well as low voltage bulk silicon technologies.