Failure Analysis of Stacked-Die Devices by Combining Non-Destructive Localization- and Target Preparation Methods
C. Schmidt1, M. Simon-Najasek1, F. Altmann1, A. Nowodzinski2, (1)Fraunhofer Institute for Mechanics of Materials, Halle, Germany, (2)CEA-LETI Minatec, Grenoble Cedex 9, France
On-going miniaturisation combined with increasing integration density and functionality leads to extreme challenges for failure localization in complex multi chip devices. Mostly, direct optical access to inner structures is not available because of the three dimensional built up. Therefore standard techniques for failure localization like emission microscopy, OBIRCH or liquid crystal thermography are limited or not useful. Furthermore, target preparation, e.g. Cross sectioning of small sized defect structures can be also challenging because mechanically polishing is not precise enough and focused ion beam techniques are unsuitable for a whole chip stack. This paper presents the combination of defect localisation by Lock-in-Thermography (LIT) and cross-section preparation at defect structures of multi-chip-modules and demonstrates a complete failure analysis flow at high ohmic chip to chip interconnects.
Challenges Facing the Detection of Leakage Current in Integrated Circuit (IC) Devices
S. L. Toh, E. Hendarto, J. Sudijono, P. K. Tan, Y. W. Goh, H. B. Lin, Q. Deng, H. Tan, L. Zhu, Q. F. Wang, H. L. Li, R. He, J. Lam, Z. H. Mai, Chartered Semiconductor Manufacturing Pte. Ltd., Singapore, Singapore
The methodology and challenges facing failure analysis in the detection of leakage current in devices were discussed. New "packaging" failure analysis methodology was proposed to help in the detection of leaky site for devices with smaller physical feature sizes.
Analysis of a Media Processor Functional Failure
A. J. Putman, Intel Corporation, Chandler, AZ
Start up and Evolution of a FEI DA 300 DBFIB for Automatic STEM Sample Preparation
J. J. Demarest1, Z. DeSouza2, (1)IBM, Albany, NY, (2)FEI, Hillsboro, OR
In the fall of last year a FEI1 DA 300 dual beam focused ion beam (DBFIB) was installed at Albany Nanotech in Albany, NY. This instrument’s purpose is to make scanning transmission electron microscope (STEM) or transmission electron microscope (TEM) samples in a highly automated fashion as well as automatic navigation to defects based on KLARF data and subsequent cross sectioning and imaging of those defects. This paper deals primarily with the difficulties and subsequent solutions to STEM sample preparation. Approximately twenty major challenges were encountered spanning hardware, software, and material sample preparation. Some of these issues will be highlighted along with their resolutions.
The Helium Ion Microscope for High Resolution Imaging, Materials Analysis, Circuit Edit and FA Applications
W. B. Thompson1, J. Notte2, L. Scipioni2, M. Ananth2, L. Stern2, D. Ferranti2, C. Huynh2, S. Sijbrandij2, L. Farkas2, L. Barriss2, C. Sanford2, (1)Carl Zeiss NTS, Peabody, MA, (2)Carl Zeiss SMT, Peabody, MA
The helium ion microscope presently has 0.3 nm resolution at a 6mm working distance. Secondary electron and backscattered ion mode images are acquired simultaneously. No sample coating is required and dielectrics can be imaged at the highest beam energy and magnification. A Rutherford Backscatter detector provides atomic level film thickness discrimination in small fields of view. A gas injection system with pattern generator gives quality, overspray free, deposition and etch capability.
Damage Induced Field Failures of Electrical Contacts
A. Munukutla, R. Rahn, J. Lewis, Intel Corporation, Hillsboro, OR
This paper discusses the failure mechanism and root cause for memory failures on one of the products. Also discussed in detail is the approach of fault isolation followed by hypothesis development & physical analysis to arrive at root cause of failure. Physical analysis included optical microscope, cross section followed by SEM analysis coupled with EDX, 2D X-ray. The failure mechanism was due to nickel oxide formation at the area of contact leading to intermittent failures
Gradient Thermal Analysis by Induced Stimulus
J. Colvin, FA Instruments, San Jose, CA
Measurement of Bit Leakages in a Functional SRAM
X. Deng, W. K. Loh, B. Pious, J. Raval, B. Khan, L. Liu, T. Lowry, D. Yoon, T. W. Houston, R. McKee, A. S. Kasper, D. Corum, Texas Instruments Inc, Dallas, TX
A direct bit leakage measurement (DBLM) scheme is proposed and implemented in 8Mb and 32Mb SRAM’s in 45nm and 32nm technologies. It allows, for the first time, direct and nondestructive measurement of various defect induced leakages in each bit in a functional SRAM. It thus enables collection of various defect induced bit leakage data for low-cost and fast failure analysis. It also enables collection of massive bit leakage data for statistical evaluation and location sensitivity assessment.
Extended Circuit Edit, Analysis and Trimming Capabilities based on the Backside Focused Ion Beam created Ultra Thin Silicon Platforms
R. Schlangen, U. Kerst, C. Boit, TUB Berlin Institute of Technology, Berlin, Germany
A full physical debug concept for Integrated Circuits (ICs) based upon backside Focused ion Beam (FIB) preparation has been developed. After creation of a back surface on ultra thin silicon (UTS) with FIB, physical functional analysis can be performed with nanoscale potential because of the short remaining interaction path, Circuit Edit (CE) can be performed in a much lager variety from one active device to others, and functional parts can be edited that even have not been contacted originally. Finally we report on increasing or decreasing transistor speed depending on depth of FIB processing, offering the unique opportuniy to accelerate slow signal paths that would make the following part of the circuit untestable or to compensate for resistance increases due to CE. All techniques are applied to a fully functional circuit which underlines the unique character of the presented approach.
Subsurface Imaging of Multi-Level Integrated Circuits Using Scanning Electron Acoustic Microscopy
L. Meng1, A. G. Street2, J. C. H. Phang1, (1)Centre for Integrated Circuit Failure Analysis and Reliability (CICFAR), National University of Singapore, Singapore, Singapore, (2)Inscope Labs, Singapore
Scanning Electron Acoustic Microscopy has been used to generate high-resolution images of subsurface features at different depths in multi-level integrated circuits. Significant improvements in SEAM contrast, spatial resolution and depth discrimination have been demonstrated.
Laser Timing Probe with Frequency Mapping
J. C. H. Phang1, L. S. Koh2, H. L. Marks3, L. K. Ross2, C. M. Chua2, (1)Centre for Integrated Circuit Failure Analysis and Reliability (CICFAR), National University of Singapore, Singapore, Singapore, (2)SEMICAPS PTE LTD, Singapore, Singapore, Singapore, (3)NVIDIA, Santa Clara, CA
Pseudo-Soft Defect Localization
P. Tangyunyong, R. McFarland, R. S. Flores, S. Pearson, M. O. Sanchez, Sandia National Laboratories, Albuquerque, NM
In this paper, we describe a modified soft defect localization (SDL) technique, PSDL (pseudo-soft defect localization), to localize pseudo-soft defects in integrated circuits (ICs). Similar to soft defects, functional failures due to pseudo-soft defects are sensitive to operating parameters (such as voltages, frequencies and temperatures) and/or laser exposures. Pass/fail states in pseudo soft defect failures are, however, not fully reversible after laser exposure or after changing operating parameters. PSDL uses the methodology of conventional SDL and/or TIVA in combination with a new scanning scheme for defect localization. An example will be shown to demonstrate the use of this technique to localize pseudo-soft defects
Software Enhanced Time Resolved Laser Assisted Device Alteration with a Non-Pulsed Laser Source
K. Erington, J. Asquith, D. J. Bodoh, Freescale Semiconductor, Austin, TX
We present a method of time-resolved laser assisted device alteration (or SDL) that uses a CW laser with no modulation. The time resolution is on the order of microseconds.
From Static to Full Dynamic Laser Stimulation
A. Deyine, THALES & CNES (French Space Agency) laboratory, Toulouse, France
Laser stimulation techniques are currently used in semiconductor device failure analysis in addition to electrical tests in order to localize defects in a device. The failure analysis in integrated circuit becomes more and more complex since electronic component integration increases. We propose to add a dimension in the dynamic analysis of integrated circuit: the time when the failure occurs. We present a new Dynamic Laser Stimulation technique involving a tester which controls the laser power (modulation, on and off), the laser position on the device and the device itself. Defects localization and electrical tests can be coupled to discriminate defects and to provide more useful information about the failure. It is the latest evolution of optical technique to provide more accurate analysis with a single set up: the Full Dynamic Laser Stimulation.
Annular Illumination and Solid Immersion
S. B. Ippolito1, H. Terada2, (1)IBM, Hopewell Junction, NY, (2)Hamamatsu Photonics, Systems Division, Higashi-Ku, Hamamatsu City, Japan
Annular illumination is a particular type of angular spectrum tailoring that can significantly improve integrated circuit analysis with an optical microscope when combined with solid immersion. We present the development, testing, and optimization of a simple and compact apparatus to implement annular illumination on a Hamamatsu iPHEMOS system. We demonstrated the improvements from annular illumination on an IBM 45nm silicon-on-insulator circuit in confocal scanning optical microscopy and widefield microscopy with an InGaAs camera.
Backside IR Raman Temperature Measurements
R. A. Falk1, T. Pham2, (1)Quantum Focus Instruments, Tukwila, WA, (2)Quantum Focus Instruments, OptoMetrix Division, Tukwila, WA
Describes Raman temperature measurement through silicon backside
Nanoprobe Capacitance-Voltage Spectroscopy (NCVS) Localization of 45nm SOI SRAM Array Bit Line Failure
T. Kane, M. P. Tenney, IBM, Hopewell Junction, NY
This paper is intended to describe the application of NCVS to localize defects in specific MOSFET devices at CA level with follow-on root cause analysis that would not have been detected using legacy methods of Focused Ion Beam (FIB) voltage contrast or scanning electron microscopy (SEM) or even atomic force probing (AFP) current imaging techniques . Localization of a FEOL defect in a discrete 45nm SOI MOSFET device in a peripheral sense amp circuit causing a paired bit line signature with follow-on transmission electron microscopy root cause analysis will be shown.
The SRAM Soft Failure Analysis with SNM & TR Characterization by Nanoprobing in Sub 45nm
J. Hong, S. Cho, Y. Han, H. Choi, S. D. Kwon, H. Kim, T. Kim, S. Son, Samsung Electronics System LSI, Yongin, South Korea
Using the Nanoprobe technique, transistor characteristic in actual SRAM cell has been directly measured. To define the root causes of marginal soft failure, characterizing transistor level has its limits to understand cell stability and failure mechanism. Moreover, as a shrink of SRAM cell dimension, Electron beam irradiation comes to an important issue. When focused electron beam at SRAM cell for a time, it is affected to change transistor characteristics, such as Vth shift and Idoff, Idsat swing. During probing with SEM based nanoprober, to get correct data, it has to reduce electron beam influence at all possible. As a probing at Metal1 layer, it is possible to avoid electron beam influence, furthermore it allows the coupled analysis of cell stability and TR characteristics. This paper presents the process of measuring SNM (static noise margin), WNM (write noise margin) with 6 pin nanoprober, and characterization & analysis of SRAM cell stability through the case study of 45nm devices SRAM soft failure.
Electrical Characterization of Different Failure Modes in Sub-100 Nm Devices Using Nanoprobing Technique
E. Hendarto, S. L. Toh, J. Sudijono, P. K. Tan, H. Tan, Y. W. Goh, L. Zhu, Q. Deng, H. Lin, R. He, H. Li, Z. Mai, J. Lam, Chartered Semiconductor Manufacturing Pte. Ltd., Singapore, Singapore
This paper presents the effectiveness of the nanoprobing technique in isolating nanoscale defects in hard-fail cases. In two of these cases, the SEM Passive Voltage Contrast (PVC) technique failed to identify the defect. Apart from identifying defective nickel silicide (NiSi) and poly-contact short issues, nanoprobing also successfully isolated the resistive contact location in a large Electrical Test (ET) structure. Such was the usefulness of the nanoprobing technique that greatly assisted the identification of failure mechanisms and thus improvement of device yield.
A Transistor Level Failure Analysis Via Nano- Probing and Junction Stain TEM to Reveal 65nm Device Lightly Doped Drain Profile Abnormality
J. Su1, S. Liang1, Y. Wen1, M. Yang1, L. Wu1, C. Niou1, X. Chen2, G. Zhao3, (1)Semiconductor Manufacturing International (Beijing) Corp, Beijing, China, (2)Semiconductor Manufacturing International (Shanghai) Corp, Shanghai, China, (3)Semiconductor Manufacturing International (Beijing) Corp, Shanghai, China
This paper incorporates Nano probing technique with junction stain Transmission Electronic Microscopy (TEM) to reveal the subtle doping defect affecting the Static Random Access Memory function in the 65nm generation node. Device malfunction relating to lack of the Lightly Dope Drain (LDD) implant induced by inconspicuous spacer defect was determined by the combined method.The combined method is a powerful alternative to reveal the SRAM fail caused by doping issue.
FAMOS Fail Bit Verification /Characterization Via NanoProbe
M. A. Dexter1, R. E. Stallcup2, S. Gunturi3, (1)Texas Instruments, Inc., dallas, TX, (2)Zyvex Corporation, Richardson, TX, (3)Texas Instruments, Inc., Dallas, TX
Global Die Ultra-Thin Silicon for Backside Diagnostics and Circuit Edit
E. O'Donnell, D. Scott, Intel Corporation, Folsom, CA
Paper will discuss how to achieve a uniform silicon thickness of 10um across an entire silicon sample to enable circuit edit and optical probing applications. Paper will further discuss the advantages of this approach and how previous concerns of mechanical instability and thermal management have been resolved.
Methods for Quantifying FIB Milling Acuity
C. Rue, FEI Company, Hillsboro, OR
This work attempts to move beyond the simple metrics of imaging resolution and minimum spot size, and identify badly-needed tests that characterize the performance of a FIB column under "real-world" conditions. Special attention is given to High Aspect Ratio (HAR) vias, but other tests are also examined.
Novel Dielectric Etch Chemistry for the Next Generation of Circuit Edit: Delicate to Low-k Dielectrics and Silicon
V. V. Makarov, L. Krasnobayev, Tiza Lab, LLC, Milpitas, CA
Novel efficient Dielectric Etch solution for Circuit Edit is presented allowing, in contrast to XeF2, to avoid spontaneous (unintentional) etching/corrosion of silicon and sensitive low-k dielectrics. The chemistry can also be used to trim diffusion structures vertically or laterally for CE or device analysis. Unlike XeF2 the new etchant has higher etch control to endpoint on silicide that can be beneficial for newer CE methodologies.
A Versatile Design of Solid Immersion Lenses in Bulk Silicon Using Focused Ion Beam Techniques
P. Scholz1, U. Kerst1, C. Boit1, C. C. Tsao2, T. Lundquist2, (1)Berlin University of Technology, Berlin, Germany, (2)DCG Systems, Fremont, CA
Solid immersion lenses (SILs) are a promising solution when resolution enhancement for backside analysis of semiconductor devices is needed. This work presents a way of creating refractive SILs within a short processing time in the bulk material and also the ability to remove them for a further analysis of the same area of the sample. This way the advantages of SILs placed on the surface and created in the bulk material with FIB can be combined.
Localized Epoxy Layer Formation on Surface Defect Using a Micro-brush in a Plucking System
K. L. Lin1, J. S. Luo2, J. D. Russell2, (1)Inotera Memories Inc., Taoyuan, Taiwan, Taoyuan, Taiwan, (2)Inotera Memories, Inc., Taoyuan, Taiwan
A novel micro-brush method to cover a defect with a micro-layer on the target’s surface using a micromanipulator of a plucking system has been introduced and successfully applied in the application of surface defect analysis without any damage or localization problem. Various sizes of micro-brushes, ranged between 10 and 330 ìm, were chosen to deal with different sizes of surface defects. The micro-brush method can be used for both in-film and on-surface defects.
Deterministic Polishing Applications In Failure Analysis
M. E. Kimball, Maxim Integrated Products, Inc., Hillsboro, OR
The paper shows how deterministic polishing (a technique taken from the optics industry) can be used to improve surface polishing. Computer simulations of the polishing process were used to help optimize the polishing results. The simulation results also showed how "standard" polishing approaches can be improved.
Near-Infrared Microscopy In Semiconductor Failure Analysis Aplications
T. B. Davis, R. R. Reagan, T. Jiang, Y. Sun, Micron Technology, Boise, ID
This paper will present a discussion of NIR and laser scanning confocal near-infrared microscopy, sample preparation for NIR microscopy, and will emphasize examples of laser scanning confocal NIR microscopy in the measurement and failure analysis of silicon samples typical to the semiconductor industry.
Non-Destructive Failure Analysis in Organic Thin-Film Transistors
S. T. Liu1, T. C. Liu1, M. L. Chang1, K. T. Chiang1, S. P. Chiu1, J. Lin1, P. Y. Lo2, P. W. Li2, (1)Integrated Service Technology Inc., Hsin-chu, Taiwan, (2)Department of Electrical Engineering, National Central University, Taoyuan, Taiwan
New approaches of failure analysis on OTFTs are reported in this study. Successful detection and localization of defects in OTFTs inspected as voids are carried out by using SAM. The physical verification has been done by cross-section TEM with wonderful preparing the OTFT sample by DB-FIB. Moreover, we found that the device leakage in OTFTs arrays is caused by gate metal elongation. The leakage sites can be observed and located precisely by OBIRCH . Those failure modes inside of OTFTs have observed and discussed is particular.
Low Temperature O2 Plasma Process for Scanning Capacitance Sample Preparation
D. W. Schulte, T. McMahon, D. D. Hall, M. Johnson, W. Stickle, C. Sanders, G. Long, Hewlett Packard, Corvallis, OR
Experimental results demonstrated a low temperature O2 plasma processing treatment can produce an oxide of sufficient quality to produce good scanning capacitance measurement results. To minimize surface contamination during the plasma process it was necessary to optimize the plasma etch power and process pressure to reduce sidewall sputtering in the system. The optimal process conditions using a PlasmaTherm 790 etch system were determined to be a 15 minute plasma treatment at 20sccm O2, 100W, and 1000mTorr pressure. The best results were obtained by processing samples on a bare silicon wafer after performing an O2 chamber clean. Although this process results in some trace fluorine and carbon surface contamination, this appeared to have no impact on the SCM signal.
Comparative Failure Analysis of Photovoltaic Arrays
J. Colvin, FA Instruments, San Jose, CA
Analysis of poly-Si thin film solar cells by IR-LBIC
M. Boostandoost1, L. Hao-Peng1, U. Kerst1, C. Boit1, S. Gall2, (1)Technische Universität Berlin, Berlin, Germany, (2)Berlin Helmholtz Center, Berlin, Germany
The light collection properties of thin film a-Si/p-Si solar cells with interdigitated mesa structure have been locally analysed in the infrared and compared to the visible spectrum using Light Beam Induced Current (LBIC) and Electroluminescence, band to band recombination in forward bias (EL) and intraband relaxation in reverse bias (ELR). The low absorption rate of IR light leads to a highly efficient collection at the corners of the mesa if the etch shape allows to couple the light horizontally into the cell, and to a reduced current when the laser is scanned over the active volume due to IR transmission and absorption properties of TCO and amorphous and thin poly Si layer.
Failure Analysis of Breakdown Sites in Silicon Solar Cells
O. Breitenstein1, J. Bauer1, J. M. Wagner1, N. Zakharov1, A. Lotnyk2, (1)Max Planck Institute of Microstructure Physics, Halle, Germany, (2)Christian-Albrecht-University, Kiel, Germany
In a solar module about 36 cells are connected in series. Only if they all have the same illuminated current-voltage (I-V) characteristics, their generated voltages simply add up. However, if one of these cells is shadowed or broken, the other cells may bias this one in reverse direction to up to -18 V. If then a large reverse current flows, which may be as large as the short circuit current of the other cells (typically 7 A), this cell dissipates a lot of heat and the module may be destroyed thermally. According to its base doping concentration of 1016 cm-3, a solar cell should undergo avalanche breakdown at -50 V and above. However, in reality breakdown may occur already at -10 to -15 V. Therefore the electric breakdown behavior of solar cells is an important reliability aspect and must be studied in detail. In this investigation the dominant breakdown sites in industrial multicrystalline Si solar cells are localized by lock-in thermography (LIT) under reverse bias. Special LIT techniques allow us to image the temperature coefficient, the slope (steepness) of the breakdown current, and the avalanche multiplication factor locally. The distribution of grown-in recombination-active crystal defects is obtained by electro¬luminescence (EL) imaging. Two dominant breakdown mechanisms are identified, which are breakdown at recombination-active crystal defects, showing a relatively soft breakdown, and avalanche breakdown at dislocation-induced etch pits, which occurs very steep (hard breakdown) and dominates in our cells at high reverse bias.
Approaches to Photovoltaic Systems Reliability
J. Granata, Sandia National Laboratories, Albuquerque, NM
Writing Better Research Reports
T. B. Davis, Micron Technology, Boise, ID
In answering the question of how can we write better research documents and reports, this paper will present a review of current research to discuss 1) the needs of each group involved with research documents and reports; 2) the difference in expectations between readers and writers; 3) the techniques used to teach report writing; and 4) what makes an effective report. The conclusion of this paper will form a generalized statement of the factors that lead to better-written research documents and reports and will point out areas of consideration for future research.
A New Failure Analysis Flow of Gate Oxide Integrity Failure in Wafer Fabrication
C. Changqing, H. Younan, Chartered Semiconductor Mfg Ltd, Singapore, Singapore
As device feature size continues to shrink, the reducing gate oxide thickness put more stringent requirement on gate dielectric quality in terms of defect density and contamination concentration. As the result, it becomes more difficult in analyzing gate oxide integrity and dielectric breakdown failures in wafer fabrication. Using traditional FA flow and methods, the root cause may be unclear, although some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. In this paper, we will propose an new failure analysis flow of the GOI failure to improve FA’s success rate. In this new proposed flow, both chemical method (Wright Etch) and SIMS analysis techniques are employed to identify root cause of the GOI failures. In general, the shape of the defect might provide information of the GOI failure, whether related to PID or contamination. However, these Wright etch results are inadequate to answer the questions of whether the failure is caused by contamination or not, what is the contaminant and where it comes from. From the Wright etch results; GOI failure can be attributed to contamination or PID. If the failure is confirmed to be due to contamination, SIMS is used to further determine contamination source at ppm-ppb level. A real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made from stainless steel.
Instrumental Discrepancy and Relation of Stress Condition
Y. Satirakul, T. Butngam, S. Phunyapinuant, Spansion (Thailand) Limited, Nonthaburi , Thailand
Doping Profile Inspected by SEM Dopant Contrast, Wet Stain and SCM
P. F. Chou, UMC, Hsinchu, Taiwan
The techniques of doping profile inspection, such as SEM dopant contrast, SEM wet stain and SCM techniques have been widely used in failure analysis for implant root causes identification. The applications of real FA cases and advantages/disadvantages will be discussed and demonstrated in this paper. To sum up, SEM dopant contrast is the most convenient method for doping profile inspection, and SCM is the best method for low doping profile observation.
Case Study: Failure Analysis of Functional Shmoo Hole with Laser Voltage Probing
S. H. Lee1, Y. W. Lee1, K. T. Lee1, C. Y. Choi1, H. W. Shin2, Y. S. Ng3, T. Lundquist3, (1)Samsung Electronics co. Ltd, Young-in, South Korea, (2)Neosem Inc., Suwon, South Korea, (3)DCG Systems, Fremont, CA
Using the LVP system, signals were probed from transistors operated at ~1.0V. With these signals, we were successful in completing the functional shmoo hole failure analysis. What were critical to the success of this failure analysis were the ability to measure the signals at low operating voltages within a short amount of time, the ability to achieve the spatial resolution required to probe within a 65nm flip-flop and the ability to detect a 400 ps glitch. The LVP technology should continue to provide signal probing solutions as fabrication process technologies continues to shrink to 45 nm and 32 nm where operating voltages are even lower. The high bandwidth performance of the LVP systems provides for analyzing signals like the “glitch”.
In Situ Polyimide Removal Using Modified Decapsulator
C. RAMACHANDRA1, S. B. MACHAIAH1, C. U. GOWDA1, D. JAYPAL1, S. K. Dash2, (1)TESSOLVE SERVICES PVT LTD, BANGALORE, India, (2)ISRO Satellite Centre, Bangalore, India
An alternative method for polyimide removal is presented. The method requires modification of commercially available dual acid decapsulator.
The Mechanism and Application of Surface Effect On e-Beam Voltage Contrast and Dopant Contrast
L. L. Lai1, H. Gao2, H. Xiao3, (1)Semiconductor Manufacturing International Corporation, WuHan, HuBei, China, (2)WuHan XinXin Semiconductor Manufacturing Corp., WuHan, HuBei, China, (3)Hermes Microvision, Inc., San Jose, CA
We had a series of experiment and observation to investigate the application for the surface effect on the voltage contrast and dopant contrast. The in-line process gave an example of detection for the flatness in post-WCMP by way of e-Beam VC inspection. Regarding of the dopant contrast with surface effect, we are able to see doping distribution directly by SEM.
Back-End-of-Line Quadrature-Clocked Voltage-Dependent Capacitance Measurements
S. V. Polonsky, P. Solomon, E. Shiling, L. Economikos, M. Bhushan, M. Ketchen, IBM, Yorktown Height, NY
We compare different dc current-based integrated capacitance measurement techniques in terms of their applicability to modern CMOS technologies. The winning approach uses quadrature detection to measure mutual Front-End-Of-Line (FEOL) and Back-End-Of-Line (BEOL) capacitances. We describe our implementation of this approach, Quadrature-clocked Voltage-dependent Capacitance Measurements (QVCM), and its application to 45 nm node BEOL: wire capacitance variability measurements for analog design, and capacitive test structure to measure the effect of metal pattern density on Chemical-Mechanical Polishing (CMP).
The Novel TEM Sample Preparation Approach for Targeted Via with Barrier/Cu Seed Layer Inspection
W. F. Hsieh, S. H. Tseng, B. M. She, UMC, Tainan County, Taiwan
In this study, a FIB-based cross section TEM sample preparation procedure for targeted via with barrier/Cu seed layer was introduced. The dual beam FIB with electron beam for target location and Ga ion beam for sample milling was the main tool for the targeted via with barrier/Cu seed layer inspection. With the help of delicate operation of FIB and epoxy layer protection, the cross section TEM results of targeted via with barrier/ Cu seed layer could be checked. This approach was used into the Cu process integration performance monitor. All these TEM results will be very helpful in process development and yield improvement.
Decapsulation Techniques for Cu Wire Bonding Package
D. Meng, J. Rupley, C. McMahon, LSI, Fort Collins, CO
Cu is being evaluated as an alternative to conventional Au as wire bonding material in recent years mainly because of its potential for significant cost reduction (up to 90%)1. Additionally Cu wire boning has better electrical, thermal and mechanical performance over Au wire bonding. However, a package with Cu wire bonding brings unique reliability issues for the package as well as challenges for failure analysis. A primary challenge for the failure analysis is the process to decapsulate a device with Cu wire bonding. In is paper, we will present our decapsulation solutions including wet chemical etch, plasma etch, laser ablation and the combination of these techniques.In a summary, Cu wire bonding package could be decapsulted using wet chemical etching with a good quality with well controlled etching time and temperature. Further, the plasma etching for Cu wire bonding package could be shorted to less than one hour by using laser ablation removing most of encapsulant mold compound.
Evaluation Trial of MEMS Devices by LSI Process Diagnostics
W. Shimizu, Oki Engineering Co., LTD., Tokyo, Japan
We have advocated "LSI Process Diagnostics system" as a technique detecting the danger element that can cause the breakdown of LSI beforehand. This time, we describe the modification of "LSI Process Diagnostics system" for the MEMS device and evaluation results.
A Novel Technique of Device Measurement After Cross-Sectional FIB in Failure Analysis
C. C. Chang1, J. C. Lin2, W. S. Wu3, C. L. Chang1, C. Y. Tsai4, (1)UMC, Tainan, Taiwan, (2)United Microelectronics Corporation, Hsin-Chu, Taiwan, (3)United Microelectronics Corporation, Ltd., Tainan County, Taiwan, (4)UMC, Tainan County, Taiwan
(1) a novel technique of device measurement by using C-AFM or Nano-Probing system after X-S FIB inspection has been developed. (2) This new technology provides a good chance for FA analysts to have a device characteristic study before TEM sample preparation. (3)High evidence electrical measurement result can be provided to diagnose if the suspected failure site is the real failure site or not. (4)Furthermore, the sample can continuously be analyzed by following TEM without any impact.
Effectiveness of Nanoprober in Detecting Single / Multiple Bit Flash Data Gain & Data Loss Failures
R. Medikonduri, Texas Instruments Incorporated, Stafford, TX
Nanoprobing method is effective in identifying an anomaly irrespective of whether a passive voltage contrast is seen or not. Knowing the nanoprobing method of chasing an anomaly in flash memory when no PVC seen or no leakage seen by AFM, will lead to higher FA success rate. Successful FA leads to prompt fixing of the issues in fab. Corrective actions in the fab, lead to lower defective units. Customers are kept happy with lower defective units and thus, the slogan “KEEP CUSTOMERS HAPPY” is justified.
Interconnect Immobilization Process for Failure Analysis
J. Schuchman, J. K. Willis, Intel Corporation, Hillsboro, OR
The poster presents a sample preparation methodology called epoxy freeze technique for failure analysis intermittent dimm connector memory problems at Printed Circuit Board Assembly level.
EFFECTIVENESS of Non Destructive Physical Analysis Method Using X-Ray CT Imaging
A. Mizoguchi, K. Takeuchi, Mitsubishi Electric Co., Kamakura, Japan
In this paper we will discuss it concerning the following two items from the viewpoint of the quality assurance.1.The method of the screening for fake parts. 2.Effectiveness and consideration in reliability evaluation examination using X-rays CT image
Failure Analysis Investigation Leading to a Yield Enhancement On the Production Units
R. Medikonduri, Texas Instruments Incorporated, Stafford, TX
The probable bad units were prevented to be shipped to the customer. The yield is enhanced by implementing the containment and corrective actions on the ATE by increasing the programming pulses to program the bit harder and by adding margin ‘0’ read besides read verify. It is also been found that the location of the selected source while nanoprobing the flash bit nearer to the drain contact is very important especially when the source sheet resistance is higher. Lastly, the impact of plasma etching during the deprocessing of the die, on the programmed bit is found. The plasma etching seems to unintentionally erase the programmed bit.
Fail Mechanisms Causing Single Bit Flash Data Gain in Flash Memory
R. Medikonduri, Texas Instruments Incorporated, Stafford, TX
Knowing the failure mechanisms properly, lead to prompt corrective actions in the Fab. Corrective actions in the fab, lead to lower defective units. Customers are kept happy with lower defective units and thus, the slogan “KEEP CUSTOMERS HAPPY” is justified.
Picosecond Single-Photon and Femtosecond Two-Photon Pulsed Laser Stimulation
V. Pouget1, E. Faraud2, K. Shao2, S. Jonathas2, D. Lewis2, D. Horain3, G. Haller4, V. Goubier4, B. Picart5, (1)IMS laboratory, University of Bordeaux, Talence, France, (2)IMS, University of Bordeaux, Talence, France, (3)PULSCAN, Talence, France, (4)STMicroelectronics, Rousset, France, (5)ATMEL, ROUSSET, France
OBIC Measurements without Lasers or Raster-Scanning Based On Compressive Sensing
T. Sun, G. L. Woods, C. Li, Y. Zhang, K. Kelly, M. F. Duarte, Rice University, Houston, TX
Laser-based failure-analysis techniques such as optical beam-induced current (OBIC) or optical beam-induced resistance change (OBIRCH) involve scanning a focused laser beam across a sample by means of a laser scanning microscope (LSM). In this paper, we demonstrate a new method of obtaining the same data without requiring a laser or an LSM. Instead, we employ new techniques from the field of compressive sensing (CS). We use an incoherent light source and a spatial light modulator in an image plane of the device under test, supplying a series of pseudo-random on/off illumination patterns (structured illumination) and recording the resulting electrical signals. Advanced algorithms allow us to reconstruct the signal for the entire die. Using CS techniques leads to advantages in throughput and potential reductions in system complexity. We present results from OBIC measurements on a damaged device and discuss extensions to other techniques such as OBIRCH and also optical emission.
Development of Laser-Based Variation Mapping Techniques – Another Way to Increase the Successful Analysis Rate On Analog & Mixed-Mode ICs
M. A. Sienkiewicz1, K. Sanchez2, L. Cattaneo3, P. Perdu2, A. Firiti1, O. Crepel4, D. Lewis5, (1)Freescale Semiconductor, Toulouse, France, (2)CNES - French Space Agency, Toulouse, France, (3)CNES, Toulouse, France, (4)Freescale Semiconductor SAS, Toulouse, France, (5)IMS laboratory, University of Bordeaux, Talence, France
The failure localization on analog & mixed mode ICs in functional mode (AC signals) has became challenging in the last few years. Due to an increasing integration, and therefore of the complexity of these devices, the number of defects, especially those named “soft”, raised considerably. An experience with the classical Dynamic Laser Stimulation techniques showed some limitations when applied to analog & mixed-mode devices. The SDL (Soft Defect Localization) technique based on two state output signals allows us to localize only the most sensitive devices. The defect in this type of circuits, which are very sensitive to the laser beam, is often characterized by a weaker sensitivity than that of “healthy” regions. Hence, xVM (Variation Mapping) techniques were introduced to map some parameters in analog way (different sensitivity levels are visualized). To date, the Delay and the Phase Variation Mapping techniques were published. We have already had some interesting results by using these techniques but not every “soft” defect case study could be resolved in that way. In this abstract we propose to look at the different parameters which characterize an analog signal and can be used as an input for the laser mapping. By applying a simple setup, without any additional sophisticated tool, we will show on a “golden” commercial device the added value of this analysis. Moreover, we will discuss its advantages and drawbacks.
UV Emission Microscopy Development for High Band Gap Components
M. Bouya1, D. Carisetti1, J. C. Clement1, B. Lambert2, P. Perdu3, N. N. Labat4, N. N. Malbert4, (1)Thales Research and Technology, Palaiseau, France, (2)UMS, Orsay, France, (3)CNES - French Space Agency, Toulouse, France, (4)IMS Laboratory, Bordeaux, France
GaN based high electron mobility transistors are actually of major interest due to their high power level performances at high frequenciess. A UV microscopy technique has been developed due to high band gap of these transistors and to locate high electrical field in Drain Source space.
Studies On A Qualification Method (OSAT) of Microchip Al Bondpads in Wafer Fabrication
R. Ramesh, H. Younan, Chartered Semiconductor Mfg Ltd, Singapore, Singapore
Al bondpad is a very important constituent of an IC microchip, even in advanced technologies such as 65nm, 45nm, 40nm & 32nm/28nm. As the bondpads are used to communicate, electrically, with other parts of circuitry, its surface qualification becomes very important in order to reduce/eliminate non-stick on pad (NSOP) problem during assembly process. It is well known fact that particles, Si-dust contaminations, corrosion-induced defects and underetch residue may contribute to NSOP. In authors’ previous studies, the pinholes/defects/underetch residue due to galvanic corrosion (Hua et al, IFTFA1998, 2000 & 2006), fluorine-induced corrosion (Hua et al, IFTFA2002, 2003 & 2008), underetch of wafer fab process (Hua et al, IFTFA1999) and Si dust of wafer die sawing (Hua et al, IFTFA2006) have been studied & discussed. In this paper, a qualification method of microchip Al bondpads will be introduced. According to this method, a good quality Al bondpad should be defect free, with low contamination level (such as fluorine and carbon contamination should be within a control limit) and with a passivation layer on bondpad surface so as to prevent bondpad corrosion. The OSAT (Optical, SEM, Auger and TEM) failure analysis method is recommended for the qualification of Al bondpads. A good quality Al bondpad will help to eliminate NSOP in wafer fabrication.
Degradation Analysis of Thick Film Chip Resistors
B. P. Sood, D. Das, M. H. Azarian, M. Pecht, CALCE, University of Maryland, College Park, MD
Negative resistance drift in thick film chip resistors at high temperature and high humidity application conditions was investigated. The paper reports investigation of possible causes including current leakage paths on the printed circuit board, delamination between the resistor protective coating and laser trim and, possibility of silver migration or copper dendrites formation.
Conductive Filament Formation in Printed Circuit Boards – Effects of Reflow Conditions and Flame Retardants
B. P. Sood, M. Pecht, CALCE, University of Maryland, College Park, MD
Conductive filament formation is an electrochemical process, which requires the transport of a metal through or across a nonmetallic medium, under the influence of an applied electric field. Previous studies, along with analysis and examinations conducted on failure sites in printed circuit boards due to CFF have shown that the conductive path is typically formed along delaminated or debonded fiber glass and epoxy resin interfaces. The advent of increas-ing board processing temperatures, dramatic miniaturization of electronic circuits and trend toward compact electronic devices has lead to increase in reliability concerns due to CFF failures. This paper is a result of an year long study to study the effects of reflow temperatures, halogen-free flame retardants, glass reinforcement weave style and conductor spacing on times to failure due to CFF.
Driving Fracture Mechanisms for Ground Silicon Dice
R. Dugnani1, M. Wu2, (1)Exponent Failure Analysis Associates, Menlo Park, CA, (2)Edwards Lifesciences, Irvine, CA
The recent increase in utilization of bare silicon integrated circuits (ICs) is largely due to the booming in the consumer markets of digital devices such as MP3 players, cellular phones, digital cameras, PDAs, etc. Due to continuous effort in miniaturizing these devices, silicon dice are often mounted on boards without encapsulation. In addition, silicon die commonly need to be mechanically thinned in order to fit into compact devices. The thinning of the wafers is normally carried out by mechanical grinding, a process that naturally weakens the silicon by introducing micro-cracks at its surface. The utilization of thin silicon die in combination with the lack of mechanical protection has makes of bare dice a typical failure mechanism in the IC industry. The current work presents results from strength characterization of silicon chips using a miniaturized four-point bending test fixtureAs expected, the strength is affected by grinding direction on silicon chip’s surface. Three distinctive fracture mechanisms associated with grinding angles were observed. Modeling of the expected fracture strength based on flaw-size SEM survey was found to correlate well with data from testing.
Ultimate Resolution for Current Localization by Means of Magnetic Techniques
F. Infante1, P. Perdu2, D. Lewis3, (1)Centre Nationale d'Etudes Spatiales (CNES), Toulouse, France, (2)CNES-French Space Agency, 31401 Toulouse Cedex 9, France, (3)IMS laboratory, University of Bordeaux, Talence, France
As the new electronics technologies shrink more and more, the need for new defect localization techniques has arisen. The Magnetic Microscopy is a promising technique which has however strong limitations when scanning currents far from the probe. We developed a new methodology, consisting to evaluate the correlation between the measurement and a set of simulations, which increase the technique resolution of a factor comprised between 10 and 20.
Enhanced De-Packaging and Chip Access
K. S. Wills, Independent Consultant, Sugar Land, TX
Chip Scale Package and its FA Challenges
S. Li, Spansion Inc, Sunnyvale, CA
Flip Chip and Backside Analysis Techniques
E. I. Cole Jr., Sandia National laboratories, Albuquerque, NM
Delayering Techniques
K. S. Wills, Independent Consultant, Sugar Land, TX
Beam-Based Defect Localization
E. I. Cole Jr., Sandia National laboratories, Albuquerque, NM
Fundamentals of Laser Based FA Techniques
A. Falk, OptoMetrix, Inc, Renton, WA
LADA and SDL Techniques
M. Bruce, Independant, TX
Magnetic Based Current Imaging for Fault Isolation in Die and Packages
L. A. Knauss, Booz Allen Hamilton, Annapolis Junction, MD
Failure Localization with Active and Passive VC in FIB and SEM
R. Rosenkranz, Fraunhofer Institute for Non-Destructive Testing, Dresden, Germany
Photonic Localization Techniques
C. Boit, TUB Berlin Institute of Technology, Berlin, Germany
FA Case Histories Using ATPG and Scan Diagnostics
K. S. Wills, Independent Consultant, Sugar Land, TX
A Practical Guide to using Scan Diagnosis for FA
M. Keim1, D. J. Bodoh2, (1)Mentor Graphics, Wilsonville, OR, (2)Freescale Semiconductor, Austin, TX
Focused Ion Beam – A Design Repair/Fault Isolation Tool
S. B. Herschbein, IBM Systems & Technology, Hopewell Junction, NY
Focused Ion Beam – A Sample Preparation Tool
K. (. Hooghan, Weatherford Laboratories, Houston, TX
FA Lab Management Overview
R. Ross, Independent, VT
Cost of FA and Debug
S. P. Maher, Oklahoma Christian University, Oklahoma City, OK
X-Ray & SAM Challenges for IC Package Inspection
T. M. Moore1, C. Hartfield1, G. Samuelson2, (1)Omniprobe, Inc., Dallas, TX, (2)Translational Genomic Institute, Phoenix, AZ
TEM Techniques for FA
S. Subramanian, Freescale Semiconductor, Inc., Austin, TX
The Role of the AFM in Yield and FA
J. Colvin, FA Instruments, San Jose, CA
Scanning Electron Microscopy
W. Vanderlinde, IARPA, College Park, MD
Ultra-High Resolution Scanning Electron Microscopy
W. Vanderlinde, IARPA, College Park, MD
Optical and Infrared FA Microscopy
J. J. McDonald, Quantum Focus Instruments Corporation, Vista, CA
Photovoltaic Systems: How Do They Work, and How Do They Fail?
J. Granata, Sandia National Laboratories, Albuquerque, NM
Introduction to MEMS: Materials and Fabrication Processes
J. A. Walraven, Sandia National Labs, Albuquerque, NM
Optoelectronic Methodologies for Characterization of MEMS and Electronic Packaging
C. Furlong, Worcester Polytechnic Institute, WPI, Worcester, MA
Diagnosing Analog Circuits
S. Ipek, Analog Devices, Wilmington, MA
Emerging Trends in Failure Modes of Nanotechnology
T. Kane, IBM, Hopewell Junction, NY
Failure Analysis of SRAM Memory
S. Gunturi1, M. A. Dexter2, (1)Texas Instruments, Inc., Dallas, TX, (2)Texas Instruments, Inc., dallas, TX
The Pivotal Role of AFP Nanoscale Failure Analysis
R. E. Mulder, Silicon Labs, Austin, TX
Failure Analysis of Present and Future DRAM Devices
M. Versen, University of Applied Sciences Rosenheim, Rosenheim, Germany
Flash Memory Failure Analysis
T. Tracy, M. Shuller, Intel Corporation, Chandler, AZ
Everything (DFT) Testing in 90 Minutes
M. Keim, Mentor Graphics, Wilsonville, OR
Yield Basics for FA
D. Albert1, T. Myers2, (1)IBM, Hopewell Junction, NY, (2)ON Semiconductor, Gresham, OR