|
||||
| Back to "Tutorial" Search | Back to Main Search | |||
| Fault Isolation | ||||
| Location: Lalique I (InterContinental Hotel Dallas) | ||||
| (Please check final room assignments on-site). | ||||
| Session Description: The haystacks are taller, and the needles are smaller. Before any understanding of a root cause can start, the failure analyst must first find the location of the defect on a failing chip. The Fault Localization Track focuses on both imaging and software techniques that can pinpoint a defective location on the failing chip. | ||||
| Session Chairs: | Ms. Susan Li Spansion Inc, Sunnyvale, CA Mr. Randal E. Mulder Silicon Labs, Austin, TX | |||
| 8:15 AM | Beam-Based Defect Localization | |||
| 10:00 AM | Break | |||
| 10:15 AM | Refreshment Break | |||
| 10:30 AM | Failure Localization with Active and Passive Voltage Contrast in FIB and SEM | |||
| 12:00 PM | Lunch | |||
| 1:00 PM | Photonic Localization Techniques | |||
| 3:00 PM | Refreshment Break | |||
| 3:15 PM | Lock-in Infrared Thermography for IC Failure Analysis | |||
| 4:15 PM | X-Ray and SAM Challenges for IC Package Inspection | |||