Integrated Circuits (IC) are finding more and more applications in the present day communication and information age. Chip interconnections, or "interconnects," serve as local and global wiring for connecting circuit elements in their logical order and distributing power. Multiple levels of wirings are required not only for faster processing but also for decreasing the wiring length of the chip interconnects. Traditionally ceramics such as Silicon di oxide and Tetraethylorthosilicate (TEOS) have been used for inter level dielectric (ILD) or insulating materials. The multilevel wiring and insulation structure needs to have highly planar constituent thin film surface in order to adhere to the strict tolerances of the IC feature dimensions. Chemical Mechanical Polishing (CMP) is process of choice used by semiconductor industry to planarize the constituent materials of the IC. During this process the materials have to withstand mechanical loading due to the applied down force and torsional forces due to the rotation. In spite of better mechanical properties and reliability, there is a need for replacement of the previously implemented ceramic materials as their electrical performance has reached a saturation point. Novel porous polymeric materials which are spin coated on a substrate have shown the requisite electrical performance for their implementation as ILD. This research evaluates and compares the mechanical properties and tribological properties of these novel polymeric materials and compares them with the existing ceramic materials. The Young’s Modulus and Hardness of the materials have been calculated using the nanoindentation technique. The dynamic coefficient of friction (COF) and acoustic emission during polishing have been measured in situ using the CETR CMP tester. The effect of polishing on the soft and inherently weak polymeric surface has been characterized using Atomic Force Microscopy and Scanning Electron Microscopy.