A Review of Defect Localization Techniques in FinFET Devices Using EBIC, EBAC, and EBIRCH with Nanoprobing

A Review of Defect Localization Techniques in FinFET Devices Using EBIC, EBAC, and EBIRCH with Nanoprobing Daminda H. Dahanayaka IBM, Albany, New York, USA daminda@ibm.com Abstract As semiconductor devices have evolved from planar to three-dimensional FinFET architectures, failure analysis has become significantly more challenging. While electrical nanoprobing can isolate failures to the device level, it is insufficient to identify defect locations within multi-fin transistors. Pinpointing failures to a single fin and specific location within that FIM is now critical for effective root cause analysis and yield learning. This talk reviews the integration of electron-beam-based techniques, Electron Beam Induced Current (EBIC), Electron Beam Absorbed Current (EBAC), and Electron Beam Induced Resistance Change (EBIRCH), with nanoprobing to enable intra-device defect localization at nanometer scale. EBIC leverages junction-related current generation to highlight defective regions, while EBAC maps conductive paths to identify opens and resistive defects. EBIRCH further enhances sensitivity by detecting localized resistance changes under electrical bias, enabling detection of subtle leakage and soft failures that are otherwise difficult to capture. Recent studies demonstrate that these combined techniques can successfully isolate defects down to exact location within individual fins in advanced FinFET devices. Modified EBIC approaches, such as two-pin configurations, improve contrast and enable identification of defective fins even in highly resistive leakage scenarios. Similarly, EBIRCH combined with nanoprobing provides high-resolution localization of resistive shorts and leakage paths, supporting targeted physical analysis. The talk will highlight how integrating these complementary techniques, along with advanced sample preparation approaches, provides a robust and scalable methodology for precise defect localization within single fins. This integrated workflow is essential for bridging electrical fault isolation and physical root-cause analysis in advanced semiconductor technologies.