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| Session 7: Failure Analysis Process 1 | ||||
| Location: South Ballroom (Worcester's Centrum Centre) | ||||
| (Please check final room assignments on-site). | ||||
| Session Description: Discussions of the FA process can include implementation of methodologies and tools to support an effective FA process, managing the FA process effectively, and successful execution of the FA process. This session includes papers discussing; definition of an effective FA methodology or process, implementation of a strategy to improve the processes of FA tool development, a system to track failures and help decision making regarding FA, and solutions to FA capacity management. | ||||
| Editors: | Mr. Tracy Myers ON Semiconductor, Gresham, OR James Cargo Agere Systems, Allentown, PA Mr. Stanley Swieck Analog Devices, Wilmington, MA Mr. Michael Eskenazi Qualcomm Corporation, San Diego, CA Felix Beaudoin IBM Mr. Ted Hasegawa National Semiconductor, Santa Clara, CA Mr. David Vallett IBM Systems and Technology Group, Essex Jct., VT | |||
| Session Chair: | Mr. Tracy Myers LSI Logic Corporation, Gresham, OR | |||
| 3:55 PM | 7.1 | PLENARY TALK: A High-Level Purpose-Driven Decision-Based Methodology for Debug and Failure Analysis | ||
| 4:20 PM | 7.2 | Improved Electrical Failure Analysis / Fault Isolation Tool Development on Server Motherboard Platforms based on Historic Failure Modes | ||
| 4:45 PM | 7.3 | Component Diagnostic Information Exchange: Tools and Education for Intel Component Defect Reduction | ||
| 5:10 PM | 7.4 | Capacity Management Solutions | ||
| 5:35 PM | Adjourn | |||