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| Session 28: Test 3 | ||||
| Location: North Ballroom (Worcester's Centrum Centre) | ||||
| (Please check final room assignments on-site). | ||||
| Session Description: This topic area examines a variety of testing issues such as test-based fault localization and defect characterization for both logic circuits and memories. It includes the use of test systems and techniques utilized in the production environment as well those employed in system level or laboratory applications that focus on an individual component. | ||||
| Editors: | Mr. Ted Hasegawa National Semiconductor, Santa Clara, CA Felix Beaudoin IBM Mr. Michael Eskenazi Qualcomm Corporation, San Diego, CA Mr. Stanley Swieck Analog Devices, Wilmington, MA James Cargo Agere Systems, Allentown, PA Ms. Anne Gattiker IBM Corporation, Austin, TX Mr. David Vallett IBM Systems and Technology Group, Essex Jct., VT | |||
| Session Chair: | Ms. Anne Gattiker IBM Corporation, Austin, TX | |||
| 3:05 PM | 28.1 | Classification of IC Process Deformation Characteristics Using Memory Fail Bitmaps | ||
| 3:30 PM | 9.4 | Diagnosing DACS (Defects That Affect Scan Chain and System Logic) | ||
| 3:55 PM | 28.3 | Failure Analysis of Functional Failures in a Designed for FA SRAM | ||
| 4:20 PM | 28.4 | On-Die Parametric Analysis of SRAM | ||