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| Session 25: Failure Analysis Process 2 | ||||
| Location: North Ballroom (Worcester's Centrum Centre) | ||||
| (Please check final room assignments on-site). | ||||
| Session Description: Discussions of the FA process can include implementation of methodologies and tools to support an effective FA process, managing the FA process effectively, and successful execution of the FA process. This session includes papers discussing; an improved fault isolation methodology for embedded cache memory, case studies where methods and decisions led to successful FA results, a software based system integrating logical and physical analysis environments supporting an effective FA process. | ||||
| Editors: | James Cargo Agere Systems, Allentown, PA Mr. Tracy Myers ON Semiconductor, Gresham, OR Mr. Stanley Swieck Analog Devices, Wilmington, MA Mr. Michael Eskenazi Qualcomm Corporation, San Diego, CA Felix Beaudoin IBM Mr. Ted Hasegawa National Semiconductor, Santa Clara, CA Mr. David Vallett IBM Systems and Technology Group, Essex Jct., VT | |||
| Session Chair: | Mr. Tracy Myers LSI Logic Corporation, Gresham, OR | |||
| 12:40 PM | 25.1 | Multi-Level Approach for High-Precision Cache Fault Isolation - Case Study: Itanium II Low Voltage Cache Yield Improvement | ||
| 1:05 PM | 25.2 | Fault isolation for a nanometer-scale poly protrusion causing single column failure in SRAM device | ||
| 1:30 PM | 25.3 | Voltage regulator output shifts due to systematic oxide non-uniformities: failure analysis, layout and process solutions | ||
| 1:55 PM | 25.4 | Precise Defect Localization of Scan Logic Failures by Using Thermal Laser Stimulation | ||
| 2:20 PM | 25.5 | Integrating Logical and Physical Analysis Capabilities for Diagnostics | ||
| 2:45 PM | Break | |||