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| Session 9: System Level Analysis 1 | ||||
| Location: Meeting Room J3 (San Jose McEnery Convention Center) | ||||
| (Please check final room assignments on-site). | ||||
| Session Description: The 2005 system level analysis session explores unique failure modes of mixed tin lead and lead free metallurgies in PCB assembly, analysis methods for characterizing lead free FBGA drop test robustness, a proposal for more inclusive system level ESD characterization, system level failures induced by contamination outgassing, and the application of high speed camera metrology for failure analysis during PCB development. | ||||
| Editors: | Mr. Daren T. Slee Exponent, Inc., Menlo Park, CA Mr. Michael Lane Intel, Hillsboro, OR Mr. Robert Knoell Visteon Corporation, Dearborn, MI Mr. Jeff Hartsell Dell Inc., ROUND ROCK, TX Mr. Roger Bjork Dell, Round Rock, TX Mr. Jeff Birdsley Dell Inc., ROUND ROCK, TX Mr. Jan Swart Exponent, Phoenix, AZ | |||
| Session Chairs: | Mr. Jeff Birdsley Dell Inc., ROUND ROCK, TX Mr. Jeff Hartsell Dell Inc., ROUND ROCK, TX | |||
| 8:00 AM | SYMP0511.3 | Furthering the Business Proposition of a Robust System Level Failure Analysis Framework: A Focus on Enabling Product Services | ||
| 8:25 AM | SYMP0511.4 | Unique Failure Modes from use of Sn-Pb and Lead-Free (mixed metallurgies) in PCB Assembly: Case Study | ||
| 8:50 AM | SYMP0511.5 | Analysis Methods for Characterizing Drop Test Robustness of Lead-Free FBGAs | ||
| 9:15 AM | SYMP0511.6 | Developing a More Inclusive System Level ESD Characterization Methodology | ||