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| Session 2: Package Level Analysis 1 | ||||
| Location: Meeting Room J3 (San Jose McEnery Convention Center) | ||||
| (Please check final room assignments on-site). | ||||
| Session Description: Successful package level analysis is accomplished using an assortment of novel techniques and tools. The Package Level Analysis Session(s) will focus attention on several successful applications of these advanced techniques and tools to help broaden your understanding specific methods while showing you to some of the extreme limits and novel applications of tools used in defect isolation. The imaginative means and abilities of some of the industries most talented individuals will be demonstrated, along with the tools and techniques they use for effective identification and isolation of package level failure mechanisms. | ||||
| Editors: | Rajen Dias Intel Corporation, Chandler, AZ Mr. Ray Harrison Texas Instruments, Dallas, TX | |||
| Session Chairs: | Mr. Ray Harrison Texas Instruments, Dallas, TX Rajen Dias Intel Corporation, Chandler, AZ | |||
| 11:00 AM | SYMP052.9 | Stacked-Die Failure Mechanisms for an Octal, Current Input 20-Bit Analog-to-Digital Converter | ||
| 11:25 AM | SYMP052.10 | Ag-on-Ag versus Sn-on-Ag Electrical Connectors for High Current and High Vibration Applications | ||
| 11:50 AM | SYMP052.11 | Analysis of Al-over-Cu Bond Pad Hillock and Pit Hole Defects | ||
| 12:15 PM | SYMP052.12 | Die Edge Thin Film Delamination on the Bottom Die of a Stacked Chip Scale Package (SCSP) | ||