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| Scanning Probe Microscopy (SPM) User Group | ||||
| Location: Meeting Room J1-J2 (San Jose McEnery Convention Center) | ||||
| (Please check final room assignments on-site). | ||||
| Session Description: Increased performance in sub 90nm node technologies is truly achieved not just on reduced feature sizes, but also on improved device characteristics and device materials. Incorporation of thinner gate dielectric films (< 1.2 nm), introduction of high gate dielectric films replacing gate oxide films, improved mobility associated with strained silicon NFET and PFET devices and low k back end of line dielectric films have collectively enable increased performance. SPM (involving atomic force microscopy, scanning capacitance microscopy, scanning spreading resistance microscopy, conductive tunneling microscopy, conductive current imaging, etc.) offers scalable multiple capable analytical approaches for shrinking device sizes and changes in gate film thicknesses without the attendant limitations of other analytical techniques. This is an informal discussion focusing on users concerns, including AFM tip quality, share analytic problem solving techniques, and “wish lists.” Discussion topics may involve case studies, new sample preparation techniques and new applications. Participants may make informal laptop presentations with images of samples for discussion.
All attendees are welcome. | ||||
| Session Chair: | Mr. Terence Kane IBM, Hopewell Junction, NY | |||