Z. Song, IBM, Hopewell Junction, NY; S. K. Loh, X. H. Zheng, S. P. Neo, C. K. Oh, Chartered Semiconductor Mfg Ltd, Singapore, Singapore

Summary: SOI technology poses new challenges on failure analysis. For bulk silicon technology, contact-level Passive Voltage Contrast (PVC) is a powerful technique for memory failure. It can easily identify the open active contact from the normal active contacts. However, for SOI technology, active contacts land on T-Si, which is insulated from silicon substrate. Whether active contacts are open or not, they are at the same potential under e-beam or ion beam inspection because they are all floating. So, contact-level PVC technique is not suitable for SOI technology. In this paper, we will present some cases to demonstrate the application of FIB circuit edit in analysis of memory failure of SOI devices.