CMOS IC Technology has progressed for over 40 years primarily by laterally shrinking the MOSFET feature sizes and the gate-dielectric thickness (“scaling). As the 45-nm CMOS technology node is approaching, such “classical” scaling is reaching its limits. New process technologies and materials are needed to allow the 45-nm CMOS (and beyond) to be reached. In this tutorial, we will briefly survey these emerging technologies, including: Strained silicon: Hi-k gate-dielectrics; Metal gate-electrodes; Ultra-shallow S/D junctions; Atomic-layer deposition (ALD); Dual-damascene Cu/Low-k Interconnects; Advanced Lithography; Silicon-on- Insulator, and “Non-classical” IC devices.