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| Test and Logic Diagnostics | ||||
| Location: J1/J4 (San Jose McEnery Convention Center) | ||||
| (Please check final room assignments on-site). | ||||
| Session Description: | ||||
| Session Chair: | Mr. Tracy Myers ON Semiconductor, Gresham, OR | |||
| 8:00 AM | From Scan Testing to Embedded Testing | |||
| 9:30 AM | Break | |||
| 9:45 AM | Defect-Oriented Testing | |||
| 12:00 PM | Lunch | |||
| 1:00 PM | Logic Diagnostics: Techniques, Applications and Challenges | |||
| 3:00 PM | 2nd Break | |||
| 3:15 PM | FA Case Histories using ATPG and SCAN Diagnostics | |||