S. M. Elliott, M. R. LaPierre, P. R. Plourde, Fairchild Semiconductor, South Portland, ME

Summary: Backside techniques to isolate faults in integrated circuits are a common approach used by many failure analysts, and the increasing number of metallization layers of many semiconductor devices today makes backside analysis necessary. Traditionally, backside analysis involves parallel polishing the back of the package and/or die to thin and expose the die substrate. The sample is then biased in the failing mode using inverted microprobes or open socketed test board in the analytical tool of choice and near-infrared (NIR) imaging is performed. One challenge facing failure analysts today is the continuously shrinking dimensions of semiconductor devices. Semiconductor device packages are approaching the dimensions of the singulated die, as evidenced by the increasing popularity of chip scale packages (CSP). CSP devices integrate the semiconductor die and connecting leads consisting of BGA (Ball Grid Array) or LGA (Land Grid Array) into a compact footprint within the size of the semiconductor die itself. Because of this, existing backside analysis techniques on CSP devices or singulated die is not feasible since no “package” exists to secure and mount the sample during inverted electrical testing without obscuring the active area of the die during NIR imaging. This paper discusses a novel and cost effective approach to perform backside analysis on a singulated die or CSP device.