S. B. Herschbein, C. H. H. Kang, S. L. Jansen, A. S. Dalton, IBM Systems & Technology, Hopewell Junction, NY

Summary: The installation of a full wafer Dual Beam FIB on the wafer fabrication line has created the opportunity to move certain traditional failure analysis tasks out of the lab and onto the factory floor. Over the past few years numerous papers have been published on the value of the in-line FIB as an early learning tool for construction analysis and defect root-cause determination. With appropriate precautions, however, we believe substantial value can also be derived by leveraging this tool for selective circuit editing on partially processed wafers. Engineering lots that have completed the basic transistor fabrication process can be routed to the FIB for mid or back end wiring changes, then returned to the line to complete the wafer build. While we have successfully performed full logic changes in-line (cuts and conductor deposition to correct errors), this paper will discuss our extensive experience in doing simple 'deletes' to simulate memory array defects. In this procedure we ‘write’ a pattern of defects directly into a memory array at an early mask level. Electrical bit mapping of these sites upon wafer completion is then used to verify correlation between logical and physical addressing of the array. This early feedback in-line methodology has worked so well that it has almost entirely displaced the complex laboratory procedure of backside FIB memory array descramble verification.