ISTFA Home
•
Exposition
•
To Register
•
ASM Homepage
Back to "Session 17: Failure Analysis Process II" Search
Back to "Symposium" Search
Back to Main Search
Thursday, November 6, 2008 - 1:10 PM
Mis-identified Failures in FETs
M. Gores
, Hi-Rel Labotories, Inc, Spokane, WA
View in WORD format
Summary:
Discussion on how FET failures that initially appear to be caused by overcurrent conditions are actually caused by open or intermittently open circuit gates.