|
||||
| Back to "Symposium" Search | Back to Main Search | |||
| Session 17: Failure Analysis Process II | ||||
| Location: Portland Ballroom 254 (Oregon Convention Center ) | ||||
| (Please check final room assignments on-site). | ||||
| Session Description: | ||||
| Session Chair: | Mr. David Burgess Accelerated Analysis, Half Moon Bay, CA | |||
| 12:45 PM | A procedure for identifying the failure mechanism responsible for a pin-to-pin short in plastic mold compound integrated circuit packages | |||
| 1:10 PM | Mis-identified Failures in FETs | |||
| 1:35 PM | Frontside and backside analysis of surface ESD | |||
| 2:00 PM | Intermittent failures, challenges and strategies involved with finding root cause | |||
| 2:25 PM | Transient latch up analysis of power control device with combined light emission and backside transient interferometric mapping methods | |||