T. Kiyan, C. Boit, Berlin University of Technology, Berlin, Germany; C. Brillert, Infineon Technologies AG, Munich, Germany

Summary: Since scan design is a widely used methodology to improve the testability of the devices, the timing analysis of the scan chain structures is necessary to characterize the performance of a clock driven circuit. In this paper, a methodology will be presented based upon laser stimulation which localises the fault relevant sites in a scan chain cell and a comparison of continuous wave and pulsed laser operation. The pulse of the laser is externally triggered and can easily be shifted to various time slots in reference to clock and scan pattern. It is demonstrated that the technique is able to identify the most sensitive signal condition for fault injection with a better time resolution than pulse width of the laser, a significant improvement for failure analysis of Integrated Circuits.