C. Cassidy, austriamicrosystems AG, Unterpremstaetten, Austria

Summary: This paper is concerned with characterisation and failure analysis challenges posed by 3D integration of semiconductor devices, with a particular focus on wafer bonded components and Through Silicon Vias (TSV). Advantages and limitations exhibited by various different sample preparation techniques, when applied to integrated devices, are discussed. Challenges encountered with real devices are presented, along with successful solutions enabled by a precision polishing toolset (Gatan Frontier).