Successful failure analysis of DRAM components is not possible without preparative measurement techniques and electrical analysis. This presentation depicts, which testing methods fulfill the necessary conditions for a successful physical failure analysis in all stages of a product cycle, early silicon, yield improvement and customer sampling. A short introduction to the defect problems of highly integrated DRAM components will be followed by a functional description of the DRAM. Failures within the cell array are analyzed and localized by the Bitmapping technique for yield improvement. Resolution limits of the Bitmapping technique require new methods for defect localization in the periphery of the DRAM. These limits can be resolved by the TIVA and Soft-Defect-Localization (SDL) technique for early silicon analysis and customer sampling.