Flip Chip and Backside Preparation Techniques
Flip Chip and Backside Preparation Techniques
Monday, October 28, 2024: 8:00 AM
204 (Hilton San Diego Bayfront)
Summary:
State-of-the-art techniques for failure localization and design modification through bulk silicon are essential for multi-level metallization and new flip chip packaging methods. This tutorial reviews the transmission of light through silicon and sample preparation required to implement backside failure analysis methodologies. The backside preparation techniques are divided into three main categories, global Si thinning, local Si thinning/precision probe hole milling, and ultra-thin preparation.
State-of-the-art techniques for failure localization and design modification through bulk silicon are essential for multi-level metallization and new flip chip packaging methods. This tutorial reviews the transmission of light through silicon and sample preparation required to implement backside failure analysis methodologies. The backside preparation techniques are divided into three main categories, global Si thinning, local Si thinning/precision probe hole milling, and ultra-thin preparation.