The future of microelectronics hinges upon successful employment of new technologies that can meet the ever-increasing demand for smaller and faster devices. It is clear that the materials, design, and processes used in current devices can't meet this demand. Current materials have been pushed to their intrinsic limits of physical and functional reliability: structural and processing requirements have become unrealistically complex. New materials, new designs, and new processes are desperately needed to overcome such challenges, spurring fundamental research and development on many fronts. Among the many technological thrusts within the microelectronics community, the advanced interconnect is particularly challenging. The future interconnect will be required to carry higher electrical load with greater speed, yet in extremely small and complex structures. In order to cope with these conflicting demands, new materials and processes are beginning to emerge. The low-k dielectric materials combined with nanoscale Cu technology is widely considered to be a most promising avenue, however, this technology is currently facing steep challenges due to unforeseen problems new to the microelectronics industry. The heart of the problem lies in the paradoxical fact that the technology must rely on materials and structures that are intrinsically unstable. In particular, low-k materials are both mechanically and chemically unstable and have limited stability against reactions with other materials in the interconnect structure and even ambient. Extra measures are needed to enhance their stability and reliability but at the expense of complexity in structural design and processes. This paper discusses the challenges of future interconnect technologies with a specific focus on the issues addressed above. Discussion will include introduction of the current interconnect technology, future technology and the related challenges, and possible solutions.