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Monday, October 18, 2004 - 11:30 AM
FRO 1.4

INVITED: Transmission Electron Microscopy for Process Development, Manufacturing, and Failure Analysis of Semiconductor Devices

R. Rai, Freescale Semiconductor, Austin, TX

As the scaling of semiconductor devices migrates to the deep sub-micron technology nodes, structural analysis will rely heavily on transmission electron microscopy (TEM) because scanning electron microscopy (SEM) may not provide desired spatial resolution. Semiconductor companies are exploring alternative gate stack materials (high-K dielectric and metal gates), band engineering methods (using strained Si or SiGe), and alternative transistor structures like double gate MOSFET, FDSOI, FinFET, and nanotechnology. For most devices, various materials, such as Si, SiO2, Cu, Ti, TiN, Ta, TaN, CoSi2, NiSix, W, WiSix, etc., are deposited and patterned to form functional devices and interconnections. This translates into an important role of TEM as future analytical tool for assisting the development and processing of semiconductor devices. Aggressive reduction in the thickness of SiO2-based gate dielectrics brings about a number of fundamental problems, the most critical ones being reduced dielectric reliability and exponential increasing leakage (tunneling) current with decreasing oxide thickness. This has prompted an urgent search for high-K dielectrics, which requires extensive materials analyses at high spatial resolution. There are still some concerns about applying TEM for routine support of process development and manufacturing, related to small examining area, difficult to prepare sample, long turnaround time, and high cost to set up a lab. Recently, application of TEM in the failure analysis of semiconductor integrated circuits (ICs) has been driven by developments in specific-area TEM sample preparation using FIB instruments. Latest developments in the area of TEM sample preparation using FIB milling and TEM based techniques applicable for analyses of semiconductor materials and devices will be reviewed. Finally, role of TEM in process development, materials issues related to integration of NiSi in CMOS, materials issues related to high-K gate dielectrics for future technology, and failure analysis of semiconductor devices will be presented from case studies.

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