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Thursday, November 18, 2004 - 4:20 PM
26.4

"On Wafer" Design Validation through Complementary Dual-Side Circuit Editing using FIB

M. A. Thompson, Credence Systems Corporation, Sunnyvale, CA; C. Chen, C. C. Tsao, Credence Systems Inc., San Jose, CA; M. Han, H. L. Tsai, Semiconductor Manufacturing International Corp., Shanghai, China

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