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| Session 14: System Level Analysis 1 | ||||
| Location: South Ballroom (Worcester's Centrum Centre) | ||||
| (Please check final room assignments on-site). | ||||
| Session Description: Papers in this session examine techniques for and characterization of lead and lead-free BGA interconnect, system level ESD sensitivity, failure detection incorporating varying power sequencing and slew rate, and the effect of power plane shapes on inter-planar electric field intensities and associated failure mechanisms. | ||||
| Editors: | Mr. Jeff Birdsley Dell, Round Rock, TX James Cargo Agere Systems, Allentown, PA Mr. Stanley Swieck Analog Devices, Wilmington, MA Mr. Michael Eskenazi Qualcomm Corporation, San Diego, CA Felix Beaudoin IBM Mr. Ted Hasegawa National Semiconductor, Santa Clara, CA Mr. David Vallett IBM Systems and Technology Group, Essex Jct., VT | |||
| Session Chair: | Mr. Jeff Birdsley Dell, Round Rock, TX | |||
| 1:45 PM | 14.1 | Materials Characterization of Lead Free Compositions for Minimum Temperature SMT Processes at the SLI-Second Level Interconnect Solder Joint | ||
| 2:10 PM | 14.2 | Measurement of Solder Joint Strength and its Dependence on Thermal Aging in Freestanding and Board-Mounted Packages Using a Laser Spallation Technique | ||
| 2:35 PM | 14.3 | A Methodology for Characterizing System-Level ESD Sensitivity | ||
| 3:00 PM | 14.4 | Design and Process Related Failure Detection with Reliability Testing Incorporating Varying Power Sequencing and Slew Rate | ||
| 3:25 PM | 14.5 | A study of power plane shapes, their contribution to inter-planar electric field intensities, and pre-preg breakdown | ||
| 3:50 PM | Break | |||