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| Session 24: SPM Techniques 3 | ||||
| Location: Jr. Ballroom (Worcester's Centrum Centre) | ||||
| (Please check final room assignments on-site). | ||||
| Session Description: The wide range of measurements possible using Scanned Probe Microscopy make possible new FI and FA methodologies utilizing Scanning Capacitance and Conductivity Mapping. Each of these techniques can be used with extremely simple parallel lapping sample preparation to generate definative and easy to understand analysis. This session will demonstrate the power of SPM for the FA laboratory. | ||||
| Editors: | Mr. Ted Hasegawa National Semiconductor, Santa Clara, CA Felix Beaudoin IBM Mr. Michael Eskenazi Qualcomm Corporation, San Diego, CA Mr. Stanley Swieck Analog Devices, Wilmington, MA James Cargo Agere Systems, Allentown, PA Mr. Andy Erickson Multiprobe, Inc., Santa Barbara, CA Mr. Roger L. Alvis Multiprobe, Inc., Santa Barbara, CA Mr. David Vallett IBM Systems and Technology Group, Essex Jct., VT | |||
| Session Chair: | Mr. Roger L. Alvis Multiprobe, Inc., Santa Barbara, CA | |||
| 12:40 PM | 24.1 | Scanning Capacitance Microscopy at Transistor Contact Level | ||
| 1:05 PM | 24.2 | Characterization Complex Voltage Contrast Image Using Atomic Force Microscopy | ||
| 1:30 PM | 24.3 | A Novel Electrical Test by C-AFM to Differentiate Gate-to-S/D Gate Oxide Short from non-Gate Oxide Short Defect in Real Products | ||