Electrical Overstress (EOS) in its various incarnations is a constant cause of failure for integrated circuits. As circuit geometries shrink and with it a decrease in operating voltages; devices are more susceptible to EOS failure due to over-voltage or/and over-current transients. This is particularly true when devices are assembled into end-item customer board assemblies and are subjected to system level stresses. Discussions with end-item customers reveal that just reporting EOS is no longer acceptable. The purpose of this presentation is to understand the causes of EOS and ESD and understand the impact on semiconductor devices. Due to the challenge of differentiating EOS and ESD, we propose a flowchart that will, first establish a foundation of data collection for all types of failure modes. And secondly, establish appropriate data collecting protocols for verified EOS/ESD stressed devices.