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Device and Test 3
Location: Meeting Room J1 (San Jose McEnery Convention Center)
(Please check final room assignments on-site).
Session Description:

Editor:Mr. Jeremy A. Walraven Sandia National Labs, Albuquerque, NM
Session Chair:Dr. Vijay Chowdhury Altera Corp., San Jose, CA
1:00 PMElectrical Overstress (EOS) in Semiconductor Devices: How to Differentiate and Document EOS due to Over-Current or Over-Voltage Conditions (New for 2005)
1:30 PMEOS/ESD - TLP Testing of Electronic Components
3:00 PMBreak
3:15 PMOptoelectronics Failure Analysis