V. Narang, P. Muthu, AMD Singapore, Singapore, Singapore; J. Chin, Advanced Micro Devices Pte Ltd, SIngapore, Singapore; V. Lim, Institute of Microelectronics,, Singapore, Singapore

Summary: Implant related issues are hard to detect with conventional techniques for advanced devices manufactured with deep sub-micron technology. This has led to introduction of site-specific analysis techniques. This paper presents the scanning capacitance microscopy (SCM) technique developed from backside of SOI microprocessor devices for packaged products. The challenge from backside method includes sample preparation methodology to obtain a thin high qualityoxide layer, SCM parameters optimization, data interpretation and establishing repeatability. Optimization of plasma etching of buried oxide followed by a new method of growing thin oxide using UV/ozone is also presented. This oxidation method overcomes the limitations imposed due to packaged unit not being able to heat to high temperature for growing thermal oxide. Backside SCM successfully profiled both the n and p type of dopants in both dense and isolated transistors.