T. Kane, M. P. Tenney, J. Bruley, S. Boettcher, IBM, Hopewell Junction, NY

Summary: Defect localization technique for isolating voltage, frequency and temperature sensitive logic circuits in sub 90nm SOI microprocessors.This technique overcomes limitations of logic chain diagnostics in terms of resolving to discrete circuit for subsequent failure analysis. This technique permits yield enhancement learning for voltage, frequency and temperature sensitive logic failures.