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| Session 15: Yield Analysis | ||||
| Location: Ballroom B (Renaissance Austin Hotel) | ||||
| (Please check final room assignments on-site). | ||||
| Session Description: The Yield Enhancement Session highlights analysis methodologies and techniques which accelerate defect localization and isolation of yield limiting issues. Methods include scan-based failure detection to quickly isolate fail modes. Information from scan-based diagnosis is used to locate defect mechanisms and determine root cause so that corrective actions can be put in place in the process and/or design to improve yield. Soft defects pose even more challenge for scan chain diagnostics and require innovative techniques to isolate. SOI substrates also post unique failure analysis and reliability considerations. As groundrules shrink, processes mature and defect densities improve, systematic defects may be induced by design for manufacturability marginalities related to layout. Design for manufacturability can help reduce design sensitivity to process variations in addition to improving yield. | ||||
| Editor: | Ms Carol Boye IBM | |||
| Session Chair: | Ms Carol Boye IBM | |||
| 9:55 AM | Translating Yield Learning into Manufacturable Designs | |||
| 10:20 AM | Improving Yield Using Scan and DFT Based Analysis for High Performance PowerPC® Microprocessor | |||
| 10:45 AM | Yield Learning with Layout-Aware Advanced Scan Diagnosis | |||
| 11:10 AM | Defect Localization Technique for Logic Circuits in Sub 90nm SOI Microprocessors | |||
| 11:35 AM | NBTI Reliability of Strained SOI MOSFETs | |||