G. Zimmermann, Infineon Technologies Taiwan Co., Ltd., Hsinchu City, Taiwan; S. Mueller, Infineon Technologies AG, Munich, Germany

Summary: This article describes a 90nm technology SRAM soft fail analysis. Affected wafers show a large number of wafer edge dies failing for single cell cluster fails at voltages below 1.0V. The cluster fails appear in characteristic areas within a 512k dualport SRAM memory block, but do not affect the edge of the memory block. Nanoprobing was used for electrical localization at cell level by means of a Zyvex system inside a SEM and a Multiprobe AFP system. Measurements of an identical fail sample are in good agreement for both systems. We will also briefly discuss the advantages of both systems. The fail area exhibits very weak PFET IV characteristics, while the drain currents of NFET cell transistors are in the expected range. For fail visualization a junction stain was applied to a TEM lamella to delineate areas with different doping levels. Due to the difference in etch behavior of the fail and a reference area, a partially blocked source/drain (S/D) implant was identified for causing the fail.