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Thursday, November 16, 2006 - 8:50 AM
Challenges in Evaluating Thickness, Phase, and Strain in Semiconductor Devices Using High-Resolution Transmission Electron Microscopy
R. Rai, J. Conner, S. Murphy, S. Swaminathan, Freescale Semiconductor, Austin, TX
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Summary:
In this paper, HRTEM challenges related to accurate thin gate oxide measurements, interfacial layer in high-k gate dielectric, strain measurements in Si-Ge MOSFETs, and phase analysis in Ni silicide using HRTEM will be described.
