N. Wakai, Y. Kobira, Toshiba Corporation, Yokohama, Japan

Summary: Fundamental consideration for CDM breakdown was investigated with 90nm technology products and others. According to the result of failure analysis, it was found that gate oxide breakdown was critical failure mode for CDM test. High trigger speed protection device such as ggNMOS and SCR is effective method to improve its CDM breakdown voltage and an improvement for evaluated products were confirmed. However, it is expected that CDM protection designing will be in severer situation because of technology development. Down-scaling of protection device size makes technologies vulnerable and huge number IC pins of high function package gives severer CDM stress. In order to solve these problems in the product, fundamental evaluations were performed. Those are a measurement of discharge parameter and stress time dependence of CDM breakdown voltage. Peak intensity and rise time of discharge current as critical parameters are well correlated their package capacitance. Increasing stress time causes breakdown voltage decreasing. This mechanism is similar to that of TDDB for gate oxide breakdown. Results from experiences and considerations for future CDM reliable designing are explained in this report.