R. E. Mulder, Silicon Labs, Austin, TX; S. Subramanian, T. Chrastecky, Freescale Semiconductor, Inc., Austin, TX

Summary: As the minimum feature lengths for CMOS technology devices continue to shrink well below the sub-100nm threshold, the physical defects that cause device failure are also decreasing in size. The gate oxide thickness for sub-100nm technologies is typically 10-20A which is equivalent to a few mono-layers of SiO2 atoms. The smallest defect or processing anomaly in these thin gate oxides can cause a significant increase in the gate leakage resulting in device failure. Also, very subtle substrate problems in regards to doping, lattice structure defects and processing can also cause device failure. These types of defects and processing problems in sub-100nm technologies have basically become invisible to the tools that worked well to image and identify gate oxide and substrate problems in older technologies such as the Scanning Election Microscope(SEM) and Transmission Electron Microscope(TEM). Instead, these failure mechanisms will have to be identified through the electrical characterization of the failing transistor. Fortunately for the failure analysis community, the probing and electrical analysis of individual failing transistors at the sub-100nm technology level can now be performed with Scanning Probe Microscopy (SPM) technology or specifically Atomic Force Probing. This paper will demonstrate how Atomic Force Probing can be used to carefully characterize failing transistors and identify failure mechanisms to allow device/process engineers to make adjustments to the wafer fabrication process to correct the problem even if physical analysis with SEM/TEM is not able to image and identify a defect.