J. Mekkoth, M. Krishna, J. Qian, Cisco Systems Inc, San Jose, CA; W. Hsu, Y. S. Cheng, Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan; C. H. Chen, National Taiwan University, Taipei, Taiwan; N. Tamarapalli, W. T. Cheng, J. Tofte, M. Keim, Mentor Graphics, Wilsonville, OR

Summary: In this paper we present a case study of yield learning for a 130nm device with 1 Million logic gates. Significant fallout was observed for a particular test pattern in the production stuck-at test pattern set. Adaptive ATPG, layout-aware scan diagnosis, and layout analysis were used to narrow down the suspected defect site. Physical failure analysis revealed a systematic bridge defect caused by metal residue left over because of dishing caused by CMP of underlying metal layers. Increasing the polishing resulted in restoring the yield back to the anticipated levels. Furthermore a new rule was added to the deck of bridge extraction rules such that, tests can be targeted to increase the quality of the outgoing parts, and diagnosis has the extra information to isolate the defects.