D. E. L. Balacano, L. P. De La Rama, Intel Technology Philippines, Inc., Gen. Trias, Cavite, Philippines

Summary: During package qualification, a 5-die-stacked chip scale package was being marginally triggered on high stand-by current collectively known as Power ICCS failure. Affected lots are subjected to 3x reflow at 240ºC. Post reflow failures include blown_up, high standby current in Vcc pin (ISBLO), and high standby current in Vccq pin (ISBLOQ). Backside chip-outs are observed on Die 1 and Die 3 of the three failures. Electrical validation showed that only Die 3 is failing. Corner crack on Die 3 is common to the blown_up and ISBLO failing units while crack on Die 3 backside is observed to propagate toward the active area on ISBLOQ failing units. Fracture analysis results show that the crack of the three failures all originated from die backside chip-out. Thermo-mechanical model of the package shows that, by design, Die 3 generates the highest stress concentration. Results show that if chip-outs are present on the area of the die with the highest stress concentration and the unit is subjected to reflow temperature of 240ºC, die crack will propagate from the chip-out. This paper presents the unique failure mechanism observed on a 5-die-stacked chip scale package and the corrective actions applied to solve the issue.