W. Danielak, S. Waldstein, W. Machado, A. Jordan, M. Jaffer, Tundra Semiconductor Corporation, Ottawa, ON, Canada; M. Sachdev, D. Li, University of Waterloo, Waterloo, ON, Canada

Summary: Latch-up is defined as creation of an unintentional, low impedance path between power supply and ground in bulk CMOS integrated circuits (ICs). Latch-up in an IC can be destructive if the current is not restricted, hence it should be avoided at all costs. With the new ASIC designs based on the library IP (Intellectual Property) from different vendors, standard IP validation based on the test chip is not sufficient. For the analyzed case of new IC design it is worth to mention that five previous chips had used this library IP without having the latch-up problem. Unique cell combination and device operation at multi-domain power supply voltages can cause the latch-up phenomenon. The analyzed ASIC device is based on 130nm CMOS technology, operates at three power supply levels (1.2V, 1.8V and 3.3V) with two ground domains (Vsscore and VssoIO) and is assembled in 1025 pins FCPBGA (Flip Chip Plastic Ball Grid Array) package. The device failed the latch-up test on two pins (K5, L8). In order to determine the root cause, the Failure Analysis (FA) with use of backside EMMI (Emission Microscopy) was performed. It was found that the root cause of the latch-up is an abutment of two specific cells (cell C and cell D), where the N-well was grounded creating a parasitic NPN transistor sustaining the latch-up. A detail calculation of parasitic resistances from the layout revealed some differences between latching and non-latching pins. The analytical model to explain the latch-up behavior based on parasitic resistances was developed and applied successfully to root cause analysis. In final conclusions, the design recommendations on how to eliminate latch-up triggering and sustaining mechanisms were made, and DRC script was developed to check the abutment of specific cells. The paper is complete and ready for submission. Any details are available on reviewer’s request.