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Session 16: Failure Analysis Process 2
Location: Meeting Room J3 (San Jose McEnery Convention Center)
(Please check final room assignments on-site).
Session Description:
Session Chair:	Mr. David L. Burgess Accelerated Analysis, Half Moon Bay, CA
2:00 PM			Comparison of Passive and Active Voltage Contrast for Failure Localization
2:25 PM			Latch-up Root Cause Analysis for new ASIC Design
2:50 PM			Analysis of Bridge Failure between PPG and LPP in Fin Cell Transistor
3:15 PM			Silicon Dislocation Enhanced by Dynamic Voltage Stress