Y. C. Lin, M. Li, R. Chen, S. Liao, W. T. K. Chien, Semicoductor Manufacturing International Co., Shanghai, China; S. Liang, C. Niou, Semiconductor Manufacturing International (Beijing) Corp, Beijing, China

Summary: In reliability test some chips suffered functional failure. Through a series of failure analysis, the root cause of such failure is considered to be silicon dislocation across LDD area causing p-n junction leakage. However, those failed samples all passed both CP (Chip Probe) and FT (Final Test) monitor. Therefore, it is reasonable to suspect that DVS (dynamic voltage stress) may enhance minor dislocation already existed before CP and FT. To approve hypothesis mentioned before, a series experiment was designed to find the relationship between DVS and the depth of dislocation in silicon substrate. In conclusion, DVS could enhance dislocation across LDD (Lightly Doped Drain) area, which may induce reliability failure. Moreover, this finding on reliability concern will be discussed in this paper.