P. Jacob, EMPA Swiss Federal Laboratories for Materials Testing and Research, Duebendorf, Switzerland; C. Hartfield, Omniprobe, Inc., Dallas, TX

Summary: ESDFOS (ESD From Outside to the device Surface) has been intensively researched on semiconductor wafers fabricated with aluminum interconnects. ESDFOS is often misdiagnosed and the root cause of the ESDFOS physical signature, damaged passivation, attributed to “mechanical damage”. However, many of the ESDFOS-damaged passivation areas are barely visible, even by SEM, with dimensions on the passivation surface of a few microns. In previous work, a series of artificially induced ESDFOS (using a Wimshurst machine) proved that small area “mechanical impact” damage was in fact caused by electrostatic discharge into the passivation, generating interlevel shorts within the two top metal layers [1, 2]. This enabled identification of process causes of ESDFOS and development of methods to reduce it [3, 4]. ESDFOS signatures on devices with Cu metallization have not been investigated. If the ESDFOS damage signature on devices with Cu interconnect does not match the damage signature from Al interconnect devices, then ESDFOS impacts will likely not be identified. Since manufacturing steps contributing to ESDFOS on Al devices are also common for Cu technology, there was a need to investigate the ESDFOS sensitivity of Cu-technology devices.