T. Kane, M. P. Tenney, IBM, Hopewell Junction, NY; A. N. Erickson, S. Phan, Multiprobe, Inc, Santa Barbara, CA

Summary: The emergence of multiple core, high speed microprocessors in 90nm node technologies has been dominated by SRAM on-processor cache. However, by employing Logic based on-processor embedded DRAM cache in 65nm SOI applications, limitations in SRAM cache involving standby current, requirements for error correction circuity to address soft error rate (SER), and Vmin cell stability can be overcome.1-14 Reported high performance embedded DRAM 65nm SOI designs with ~ 1.5ns latency and < 2ns random cycle characteristics are enabled by strain engineered pass transistor with optimized source/drain junctions for sub-pA off currents.1-12 Implementing a deep trench capacitor design versus a plate type design for embedded DRAM cache in these SOI designs means less mask steps (with lower cost) accompanied by a significantly smaller DRAM cell size.1-2 The embedded DRAM cell size for 65nm SOI cache designs measures 0.127 ƒİm2 and for 45nm SOI cache measures 0.067 ƒİm2 . These embedded DRAM cell sizes dramatically increase cache capacity (2Mb and 4Mb cache reported) while simultaneously reducing cost, power consumption, soft error sensitivity while fitting in a smaller size footprint.1-2 The challenges to electrically characterize discrete DRAM cells as small as 0.067 ƒİm2 in these embedded 2Mb caches requiring femto amp current sensitivities are not trivial.ƒ¡ƒ&brkbar;ƒzƒ¡ƒ§ Six probers are required to contact all nodes and four AFP probers placed within a 0.067 ƒİm2 cell area with femto amp current sensitivity. DRAM cell retention time tests lasting up to ten minutes for femto-amp current sensitivities pose challenges for AFP contact measurements.